2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)最新文献

A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes 超低功耗AES s - box系统性能比较

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-02 DOI: 10.1109/PATMOS.2018.8464160

Thomas Vandenabeele, Roel Uytterhoeven, W. Dehaene, N. Mentens

引用次数: 1

Ultra-Low Power Subthreshold Quasi Floating Gate CMOS Logic Family for Energy Harvesting 用于能量收集的超低功耗亚阈准浮门CMOS逻辑系列

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8463995

M. P. Garde, A. López-Martín, D. Orradre, J. Ramírez-Angulo

引用次数: 2

A Multi-Level Power-on Reset for Fine-Grained Power Management 细粒度电源管理的多级上电复位

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464167

Andres Amaya, G. LuisE.Rueda, E. Roa

引用次数: 4

Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs 面向微处理器设计精确功率建模的跨层框架

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464153

Monir Zaman, M. Shihab, A. Coskun, Y. Makris

{"title":"Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs","authors":"Monir Zaman, M. Shihab, A. Coskun, Y. Makris","doi":"10.1109/PATMOS.2018.8464153","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464153","url":null,"abstract":"While state-of-the-art system-level simulators can deliver swift estimation of power dissipation for microprocessor designs, they do so at the expense of reduced accuracy. On the other hand, RTL simulators are typically cycle-accurate but overwhelmingly time consuming for real-life workloads. Consequently, the design community often has to make a compromise between accuracy and speed. In this work, we propose a novel cross-layer approach that can enable accurate power estimation by carefully integrating components from system-level and RTL simulation of the target design. We first leverage the concept of simulation points to transform the workload application and isolate its most critical segments. We then profile the highest weighted simulation point (HWSP) with a RTL simulator (AnyCore) for maximum accuracy, while the rest are simulated with a system-level simulator (gem5) for ensuring fast evaluation. Finally, we combine the integrated set of profiling data as input to the power simulator (McPAT). Our evaluation results for three different SPEC2006 benchmark applications demonstrate that our proposed cross-layer framework can improve the power estimation accuracy by up to 15% for individual simulation points and by ~9% for the full application, compared to that of a conventional system-level simulation scheme.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123642324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D Integration 利用时间错位优化三维集成的互连性能

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464172

Lennart Bamberg, A. Ortiz

引用次数: 1

2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) 2018 IEEE第28届功率与时序建模、优化与仿真国际研讨会(PATMOS 2018)

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/patmos.2018.8463990

引用次数: 0

A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs 一种评估系统级IP块能耗的新方法

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464149

Johannes Knödtel, Wolffhardt Schwabe, T. Lieske, M. Reichenbach, D. Fey

{"title":"A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs","authors":"Johannes Knödtel, Wolffhardt Schwabe, T. Lieske, M. Reichenbach, D. Fey","doi":"10.1109/PATMOS.2018.8464149","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464149","url":null,"abstract":"System designers often face a serious challenge when estimating the energy requirements of their system. This information is essential for the design process. Especially for IP blocks, this is hard to estimate, since the influence of the surrounding system on the IP block needs to be considered. This creates need for a multi-level simulation: The system level must be simulated in conjunction with the IP core which is at gate level. Common approaches to this problem are too low-level and slow for system design. This paper shows another method: Using transpilation from netlists to a system design language, one can generate high-level modules which simulate the logic of the IP block and collect statistics about the energy consumption at runtime, using a statistically trained energy model. This has the advantage that no external tooling or complicated setups for crossing the boundary from system-level simulation to gate-level simulation are necessary. Benchmarks show that this approach, while rather simple to implement, yields energy values much closer to the ones we obtained with a professional gate-level toolchain than with simple average case figures, when evaluated with real world stimuli.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134048151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Blade-OC Asynchronous Resilient Template ‡ This research has been supported in part by NSF Grant #1619415. Blade-OC异步弹性模板本研究得到了NSF资助#1619415的部分支持。

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8463998

Moisés Herrera, Tingyu Wang, P. Beerel

引用次数: 0

Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology FDSOI技术中低压环形振荡器的体偏和rtn诱发频移分析

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464145

E. Barajas, X. Aragonès, D. Mateo, F. Moll, A. Rubio, J. Martín-Martínez, R. Rodríguez, M. Porti, M. Nafría, R. Castro-López, E. Roca, F. Fernández

引用次数: 0

Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management 用于能量管理的电源电压和体偏压联合分析

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464159

Rida Kheirallah, J. Gallière, N. Azémard, G. Ducharme

引用次数: 0