A Multi-Level Power-on Reset for Fine-Grained Power Management

Abstract

Several proposals of power-on-reset (POR) circuits have been reported in the literature, however only a few number of them offer the possibility to have configurable reset voltage levels. This paper proposes a POR circuit with programmable voltage thresholds allowing to operate in a wide number of applications. The circuit is based on a multi-level voltage reference using native transistors, which allows to have a reduced area and power consumption. The POR is designed in a $0.18 \mu \mathrm{m}$ standard-logic CMOS technology and occupies an area of $83\mu$ m x $68\mu \mathrm{m}$. Simulations results show a robust performance regarding temperature and process variations.