Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D Integration

The vertical interconnects in 3D ICs employ through-silicon vias (TSVs), which are frequently performance bottlenecks due to their high capacitive coupling. In order to reduce it, this work analyses the effect of temporal misalignment between signals and presents an algorithm to exploit it. The approach, based on an optimal bit-to-TSV assignment and hardware-efficient codes, enables a dramatic improvement in the 3D interconnect performance. Experimental results show that the proposed mapping reduces the delay and the noise of modern 3D interconnects by about 40 %-50 %. In combination with the classical bus invert coding, an additional decrease in the energy consumption by about 15 % is obtained.