2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)最新文献

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MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core Systems 基于mems的异构多核系统突发工作负载运行时空闲能量最小化
Ali Aalsaud, Haider Alrudainy, R. Shafik, Fei Xia, A. Yakovlev
{"title":"MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core Systems","authors":"Ali Aalsaud, Haider Alrudainy, R. Shafik, Fei Xia, A. Yakovlev","doi":"10.1109/PATMOS.2018.8464152","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464152","url":null,"abstract":"Heterogeneous many-core systems are increasingly being employed in modern embedded applications for high throughput at low energy cost considerations. These applications exhibit bursty workloads that provide with opportunities to minimize system energy. Traditionally, CMOS-based power gating circuitry, consisting of sleep transistors, is used for idle energy reduction in such applications. However, these transistors contribute high leakage current when driving large capacitive loads, making effective energy minimization challenging. In this paper, we propose a novel MEMS-based runtime energy minimization approach. Core to our approach is an integrated sleep mode management based on the performance-energy states and bursty workloads indicated by the performance counters. For effective energy minimization we use a systematic optimization of the controller design parameters by adopting finite element analysis (FEA) in multiphysics COMSOL tool. A number of PAR-SEC benchmark applications are used as case studies of bursty workloads, including CPU- and memory-intensive ones. These applications are exercised on an Exynos 5422 heterogeneous manycore platform showing up to 50% energy savings when compared with ondemand governor. Furthermore, we provide all extensive trade-off analysis to demonstrate the comparative advantages of MEMS-based controller, including zero-leakage current and noninvasive implementations suitable for commercial off-the-shelf systems.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130820673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels 基于虚拟信道的2D和3D片上网络的编码感知链路能量估计
Lennart Bamberg, J. Joseph, Robert Schmidt, Thilo Pionteck, A. Ortiz
{"title":"Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels","authors":"Lennart Bamberg, J. Joseph, Robert Schmidt, Thilo Pionteck, A. Ortiz","doi":"10.1109/PATMOS.2018.8464171","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464171","url":null,"abstract":"Network-on-chip (NoC) is the most promising design paradigm for the interconnect architecture of a multiprocessor system-on-chip (MPSoC). On the downside, a NoC has a significant impact on the overall energy consumption of the system. This work presents the first technique to precisely estimate the data dependent link energy consumption in NoCs with virtual channels. Our model works at a high level of abstraction, making it feasible to estimate the energy requirements at an early design stage. Additionally, it enables the fast evaluation and early exploration of low-power coding techniques. The presented model is applicable for 2D as well as 3D NoCs. A case study for an image processing application shows that the current link model leads to an underestimate of the link energy consumption by up to a factor of four. In contrast, the technique presented in this paper estimates the energy quantities precisely (error below 1 %).","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125639494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications 一种适用于RFID应用的耐温度变化cmos电压基准
Asghar Bahramali, M. López-Vallejo
{"title":"A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications","authors":"Asghar Bahramali, M. López-Vallejo","doi":"10.1109/PATMOS.2018.8464164","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464164","url":null,"abstract":"In this paper a reference voltage circuit is presented for outdoor RFID applications. The circuit consists of a Dickson charge pump and a series of stacked diode connected CMOS devices. With this configuration we have introduced a new approach to produce a 1.515V reference voltage from a Dickson charge pump which shows robust behavior against temperature variation. Taking advantage of a harvested RFID signal rendered the circuit suitable for a wide range of applications in which energy and area constraints are of great concern. The circuit has been designed with conventional CMOS devices using a commercial 40nm technology and simulated with cadence. The proposed circuit consumes 235nW power with 88 PPM/○C temperature coefficient in temperature range of −10°C to 125°C. The total active area of the circuit is 0.00036mm2. The circuit shows +10% −12% variation from the nominal value due to process corner analysis and its PSRR(dB) is −47©915MHz.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126708485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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