2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)最新文献_第4页

PATMOS has a History of 30 Years, Being One of the First Conferences Focusing on Low Power PATMOS拥有30年的历史，是最早关注低功耗的会议之一

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/patmos.2018.8464163

{"title":"PATMOS has a History of 30 Years, Being One of the First Conferences Focusing on Low Power","authors":"","doi":"10.1109/patmos.2018.8464163","DOIUrl":"https://doi.org/10.1109/patmos.2018.8464163","url":null,"abstract":"PATMOS has a history of 30 years, being one of the first conferences focusing on low power. Starting 2018, PATMOS will be collocated with two complementary conferences, IOLTS and IVSW, forming FEDfRo, the federative event on Design for Robustness. The traditional scope of PATMOS has mainly been about the design of circuits and architectures optimized for highest performance at lowest power consumption. But meanwhile, power-efficiency has become extremely important for many more areas spreading far beyond this traditional R&D niche. Energy efficiency has become a must in the connected network of battery-operated nodes known as Internet-of-Things (IoT). Wearable devices, home appliances, vehicles and security surveillance systems mostly rely on small sensors that should ideally operate on battery charge for days or even weeks. However, current battery efficiencies do not keep up with the growing demands of IoT nodes for power, forcing us to seek novel techniques for energy harvesting and power optimization. Additionally, energy-efficient ICT (Information and Communication Technology) infrastructures are a key issue for local and global economies. Some predict that, if current trends continue, the electricity consumption caused by the Internet will increase up to 30 times in the year 2030. The strong increase of wireless communication and the growth of cloud computing require orders of magnitude more computational power.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124826278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs Torpor:用于能量收集物联网soc的功耗感知硬件调度器

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464146

P. Anagnostou, Andres Gomez, P. Hager, H. Fatemi, J. P. D. Gyvez, L. Thiele, L. Benini

{"title":"Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs","authors":"P. Anagnostou, Andres Gomez, P. Hager, H. Fatemi, J. P. D. Gyvez, L. Thiele, L. Benini","doi":"10.1109/PATMOS.2018.8464146","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464146","url":null,"abstract":"The recent growth of applications in the emerging Internet of Things field is posing new challenges in the longterm deployments of sensing devices. Currently, system designers rely on energy harvesting to reduce battery size and extend system lifetime. While some system functions need constant power supply, others can have their service adapted dynamically to available harvested energy. In this work we propose Torpor, a power-aware HW scheduler which continuously monitors harvesting power and in combination with its software runtime, dynamically activates system functions depending on the available energy. By performing a few key functions in HW, Torpor incurs a very low power overhead during continuous monitoring, while the software runtime provides a high degree of flexibility to enable different scheduling policies. We implemented Torpor on a FPGA-based prototype and demonstrated that with a sample power-aware dynamic scheduling policy, we can have a 2x or more improvement in execution rates compared to static (power-ignorant) policies. The power consumption of Torpor's always-on hardware integrated on chip is estimated to be less than 4 μW, making it a very promising power-management add-on for microprocessors used in IoT nodes.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130675793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices 可重构开关电容DC-DC转换器，用于提高物联网设备的安全性

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464158

R. Jevtic, M. Ylitolva, L. Koskinen

{"title":"Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices","authors":"R. Jevtic, M. Ylitolva, L. Koskinen","doi":"10.1109/PATMOS.2018.8464158","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464158","url":null,"abstract":"With the ever increasing number of IoT devices, security and energy efficiency have become critical constraints in circuit design. To achieve small size and energy efficiency, devices need to be supplied by on-chip regulators. The power line generates the strongest signal in the circuit, and it is exploited for both, power and electromagnetic, side-channel attacks. In this work we propose to improve the security of the on-chip switched capacitor DC-DC converters by randomly switching between different converter topologies. Random ripple size and maximum supply voltage modulate the circuit current and power consumption, making the circuit more robust against side-channel attacks. We analyze the most common converter topologies and propose reconfigurable switched-capacitor cell for the efficient implementation in CMOS technology. The results show that power and time entropy of the proposed cell are increased significantly when compared to the commonly used DC-DC converter cell. There is around 6% variation in the DC-DC switching frequency for the constant load, and additional noise is observed in the frequency spectrum of the measured signal, thus, increasing the difficulty of the attack.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124824736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs 用于延迟不敏感FPGA设计的高性能宏块的自动时序表征

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464170

Roberto Sierra, C. Carreras, G. Caffarena

{"title":"Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs","authors":"Roberto Sierra, C. Carreras, G. Caffarena","doi":"10.1109/PATMOS.2018.8464170","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464170","url":null,"abstract":"Traditional FPGA design workflow requires the complete system in order to perform timing characterization. However, high-performance digital systems implementing scientific applications frequently occupy a large area and are suitably developed following a latency insensitive design approach to achieve multi-level parallelism. The produced circuits are composed of several deeply pipelined specialized computational macroblocks and try to maximize both the operating frequency and the usage of FPGA device resources to full capacity. These goals are most appropriately attainable through a decentralized control strategy and the optimization of performance for individual blocks independently from each other. This work proposes a synthesizable virtual wrapper architecture which does not add any functionality but simulates complete system conditions for the timing characterization of individual blocks using standard low-level synthesis tools. It further presents a high-level tool to generate both the computational blocks and the wrapper from a functional specification in C language, and shows that large blocks with inputs and outputs exceeding the available number of FPGA pins can be automatically generated and characterized. In particular, results for the blocks generated for a real computational fluid dynamics application are provided.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116931076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Reservoir Computing Hardware for Time Series Forecasting 用于时间序列预测的油藏计算硬件

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8463994

E. S. Skibinsky-Gitlin, M. Alomar, E. Isern, M. Roca, V. Canals, J. Rosselló

引用次数: 7

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design 基于vhdl的四相绝热逻辑设计数字仿真建模方法

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464140

S. Maheshwari, V. A. Bartlett, I. Kale

{"title":"VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design","authors":"S. Maheshwari, V. A. Bartlett, I. Kale","doi":"10.1109/PATMOS.2018.8464140","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464140","url":null,"abstract":"In comparison to conventional CMOS (non-adiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing the 4-phase adiabatic logic designs. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function defining the four periods of the trapezoidal AC power-clock is defined in a package which is followed by designing a library containing the behavioral VHDL models of adiabatic logic gates namely; AND/NAND, OR/NOR and XOR/XNOR. Finally, the model library is used to develop and verify the structural VHDL representation of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as a design example that demonstrates the practicality of the proposed approach.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114789037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient Many-Core Heterogeneous Systems 高能效多核异构系统并发工作负载的无模型运行时管理

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464142

Ali Aalsaud, A. Rafiev, Fei Xia, R. Shafik, A. Yakovlev

{"title":"Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient Many-Core Heterogeneous Systems","authors":"Ali Aalsaud, A. Rafiev, Fei Xia, R. Shafik, A. Yakovlev","doi":"10.1109/PATMOS.2018.8464142","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464142","url":null,"abstract":"Modern embedded systems execute multiple applications, both sequentially and concurrently, on heterogeneous platforms. Determining the most energy-efficient system configuration (i.e. the number of parallel threads, their core allocations and operating frequencies) tailored for each kind of workload is extremely challenging. In this paper, we propose a novel runtime optimization approach with the aim of maximizing power-normalized performance considering dynamic workload variations. To reduce overhead and complexity, we adopt a model-free approach to runtime adaptation based on workload classification. This classification is supported by analysis of data collected from a comprehensive study investigating the tradeoffs between inter-application concurrency with performance and power under different system configurations. We conduct extensive experiments on an Odroid XU3 heterogeneous platform with synthetic and standard benchmark applications to develop the control policies and validate our approach. These experiments show that workload classification into CPU-intensive and memory-intensive types provides the foundation for scalable energy minimization with low complexity. Implementing this approach as a Linux runtime governor, we demonstrate that IPS/Watt can be improved by over 120% compared to existing approaches.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133717459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Backlight Compensation Algorithms to Improve Power Consumption in LED- LCD Displays 提高LED- LCD显示屏功耗的背光补偿算法

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464154

Konstantinos Oikonomou, Orestis Theodorakopoulos, G. Keramidas, G. Theodoridis

引用次数: 0

Memory Access Pattern Profiling for Streaming Applications Based on MATLAB Models 基于MATLAB模型的流应用内存访问模式分析

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464151

T. Goldbrunner, Thomas Wild, A. Herkersdorf

引用次数: 2

Optical and Electrical Simulations of Radiation-Hard Photodiode in 0.35μM High-Voltage CMOS Technology 0.35μM高压CMOS技术中硬辐射光电二极管的光学和电学模拟

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464156

Filip Šegmanović, F. Roger, Gerald Meinhard, I. Jonak-Auer, T. Suligoj

引用次数: 0