2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)最新文献_第3页

Multiclass Network Attack Classifier Using CNN Tuned with Genetic Algorithms 基于遗传算法的CNN多类网络攻击分类器

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8463997

Roberto Blanco, P. Malagón, J. Cilla, Jose M. Moya

{"title":"Multiclass Network Attack Classifier Using CNN Tuned with Genetic Algorithms","authors":"Roberto Blanco, P. Malagón, J. Cilla, Jose M. Moya","doi":"10.1109/PATMOS.2018.8463997","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8463997","url":null,"abstract":"Intrusion Detection Systems (IDS) are implemented by service providers and network operators to monitor and detect attacks to protect their infrastructures and increase the service availability. Many machine learning algorithms, standalone or combined, have been proposed, including different types of Artificial Neural Networks (ANN). This work evaluates a Convolutional Neural Network (CNN), created for image classification, as a multiclass network attack classifier that can be deployed in a router. A Genetic Algorithm (GA) is used to find a high-quality solution by rearranging the layout of the input features, reducing the amount of different features if required. The tests have been done using two different public datasets with different ratio of attacks: UNSW (10 classes) and NSL-KDD (4 classes). Both classifiers distinguish correctly normal traffic from attack. However, in order to correctly classify the attack, the latter works better because it can be proportionate between the different classes, obtaining a cross-validated multi-class classifier with $K$ of 0.95.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127705518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power SoC 基于fpga的超低功耗SoC快速准确评估平台

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464173

Guillaume Patrigeon, P. Benoit, L. Torres

{"title":"FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power SoC","authors":"Guillaume Patrigeon, P. Benoit, L. Torres","doi":"10.1109/PATMOS.2018.8464173","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464173","url":null,"abstract":"Accurate evaluation of Ultra Low Power Systems on Chip (ULP SoC) is a huge challenge for designers and developers. In embedded applications, especially for Internet of Things end-node devices, ULP SoCs have to interact with their environment and need self-management. For this kind of applications, modelling a complete SoC, including processor(s), memories, all the peripherals components, their interaction and low-power policies, can be very complex in terms of developments and benchmarking. In order to cope with this challenge, an approach is to implement the desired system on FPGA with a monitoring infrastructure dedicated to fast and accurate performance evaluation. In this paper, we propose a set of different tools used during the evaluation step that can also be easily implemented on the final product and used by the system itself for self-assessment to enable adaptive behaviour. Illustrated by a simple architecture implemented on an FPGA-based platform, this method brings flexible, cycle accurate, fast and reliable performance evaluation and self-evaluation, with the possibility to use the platform for low-cost prototyping.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130638475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog 基于uvm的混合信号设计验证

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464148

Nikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos

引用次数: 11

VCO Verilog AMS Model for Fast Simulation in VCO-Based ADC 基于VCO的ADC快速仿真的VCO Verilog AMS模型

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8463999

David Buffeteau, D. Morche, J. L. Jiménez

引用次数: 2

Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability 随机电报噪声诱发阈值电压变异性的最坏情况性能分析

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464147

A. Islam, H. Onodera

引用次数: 5

A 40nm Critical Path Monitor for the Detection of Setup and Hold Time Violations 用于检测设置和保持时间违规的40nm关键路径监视器

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464155

Hernán Aparicio, P. Ituero

引用次数: 1

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits 时序电路中的分级时序关键路径分析

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464176

Lembit Jurimagi, R. Ubar, M. Jenihhin, J. Raik, S. Devadze, S. Kostin

{"title":"Hierarchical Timing-Critical Paths Analysis in Sequential Circuits","authors":"Lembit Jurimagi, R. Ubar, M. Jenihhin, J. Raik, S. Devadze, S. Kostin","doi":"10.1109/PATMOS.2018.8464176","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464176","url":null,"abstract":"The conventional design techniques struggle with integration density and constantly strengthening requirements of today's nanometer technology. Timing-critical paths analysis is one of such tasks. It has applications in critical path identification, path delay fault simulation, circuit reliability analysis e.g. Bias Temperature Instability (BTI) induced aging, and in several others. In this paper, we propose a scalable simulation based hierarchical technique for explicit identification of true timing-critical paths in sequential circuits. We explore the circuits at two levels - at the flat gate-level and at a higher level as a network of modules or sub-circuits. The result of timing analysis carried out at the gate-level is used for calculating the delays on the topological critical paths through the network of higher level modules. To speed-up the module level timing analysis, the theory of Structurally Synthesized BDDs (SSBDD) is used. Experimental results demonstrate considerable speed-up of the SSBDD based timing analysis, compared to the flat gate-level analysis.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122416902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Enhanced RF Harvesting System by the Utilization of Resonant Cavities 利用谐振腔增强射频采集系统

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464175

Guillem Martinez de Arriba, E. Coskuner, J. García-García

引用次数: 0

Technical Papers 技术论文

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/ivsw.2018.8494871

L. Jürimägi, R. Ubar, M. Jenihhin, J. Raik, S. Devadze, S. Kostin, Roberto Sierra, Carlos Carreras, G. Caffarena, Dominique Morche, Amal Ben Ameur, Michel Auguin, François Verdier, Valerio Frascolla, Ertugrul Coskuner, V. A. Bartlett, Izzet Kale, Wolffhardt Schwabe, T. Lieske, M. Reichenbach, Dietmar Fey, PA Hager, H. Fatemi, J. P. D. Gyvez, Asghar Bahramali

引用次数: 29

Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates 一种用于CMOS栅极时序建模的人工神经网络方法的评价

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464162

S. Goudos, N. Karagiorgos, M. Ntogramatzi, I. Messaris, S. Nikolaidis

{"title":"Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates","authors":"S. Goudos, N. Karagiorgos, M. Ntogramatzi, I. Messaris, S. Nikolaidis","doi":"10.1109/PATMOS.2018.8464162","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464162","url":null,"abstract":"The development of reliable and fast timing models for CMOS logic gates is a significant task for the IC technology. Analytical approaches have been proposed to accelerate timing analysis while keeping the accuracy in acceptable levels. However, the complexity of the analytical modeling procedure increases as we are moving towards new technology nodes influencing mostly the provided accuracy. The artificial neural network (ANN) approach could be a solution to this complexity. In this paper, the use of ANNs for timing modeling of CMOS gates is evaluated. Several different ANNs schemes are developed, optimized and studied regarding their accuracy, resource requirements and speed. Moreover, we design a new training method by combing the Particle Swarm Optimization (PSO) a meta-heuristic algorithm in conjunction with the Levenberg-Marquardt (LM) backpropagation algorithm. The outcomes show that the new training method obtains better results that the LM algorithm. The efficiency of adopting a common neural network structure, letting the coefficients to distinguish between the different logic gates is investigated.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"87 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129865876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0