超低功耗AES s - box系统性能比较

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-02 DOI:10.1109/PATMOS.2018.8464160

Thomas Vandenabeele, Roel Uytterhoeven, W. Dehaene, N. Mentens

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引用次数: 1

摘要

本文详细介绍了采用意法半导体28nm完全耗尽绝缘体上硅(FD-SOI)技术对不同AES S-box电路进行全面比较的结果。三个经过评估的s盒子被策略性地选择，以提供最大的设计空间覆盖率。给出并分析了面积、速度、功率、能量等方面的仿真结果。此外，通过在亚阈值区域模拟电路来考虑超低功耗实现。所提出的性能比较允许加密硬件设计人员为其资源有限的AES实现选择最合适的S-box设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes

This paper elaborates on the results of a thorough comparison between different AES S-box circuits in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) technology of STMicroelectronics. The three evaluated S-boxes are strategically chosen to provide a maximum coverage of the design space. Simulation results regarding area, speed, power and energy are presented and analyzed. Further, ultra low-power implementations are considered by simulating the circuits in the sub-threshold region. The presented performance comparison allows cryptographic hardware designers to select the most suitable S-box design for their resource-limited AES implementation.

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2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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