A Reliable PUF in a Dual Function SRAM

Abstract

An SRAM Physical Unclonable Function (SRAM-PUF) is a potential solution for lightweight secure key generation, and is particularly suitable for resource-constrained security devices. An SRAM-PUF is able to generate random and unique cryptographic keys based on start-up values (SUVs) by exploiting intrinsic manufacturing process variations. For cost efficiency the available on-chip SRAM in a system can be reused as a PUF. As CMOS technology scales down, ageing-induced Negative Bias Temperature Instability (NBTI) becomes more pronounced, resulting in asymmetric degradation of memory bit cells after prolonged storage of the same bit values. This causes unreliable SUVs for an SRAM-PUF. In this paper, we investigate the bit probabilities in an instruction cache and the effect on long-term reliability. We show that the signal probability in a 32-bit ARM instruction cache has a predictable pattern. Hence, we propose a bit selection technique to mitigate the NBTI effect when an instruction cache is used as a PUF. We show that this technique can reduce the predicted bit error in an SRAM-PUF from 14.18% to 5.58% over 5 years. Consequently, as the bit error reduces, the area overhead of the error-correction is about $6 \times$ smaller compared to that without a bit selection technique.