Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines

Abstract

This paper quantitatively studies the complexities of certain strategies for Single-Event Transient (SET) mitigation, offering a variety of protection levels. Several example circuits are designed, synthesized, and evaluated in the context of this study. The impact of several error-protection techniques on performance, complexity, and power dissipation is quantified. The demonstrator designs have been mapped to an ASIC standard-cell library. Replication is used as a reference technique for comparison purposes. In addition unprotected designs are used to illustrate the impact on the overall complexity. Certain choices are found to provide excellent protection with moderate cost.