Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure

Abstract

Exploiting a good energy efficiency of standard-cell memory (SCM) and a good area efficiency of SRAM, a hybrid 2-level on-chip cache structure is first introduced as a replacement of normal SRAM caches to save the energy consumption. This paper then proposes a method for finding the best mix of SCM and SRAM, which minimizes the energy consumption of the hybrid cache under a cache area constraint. The simulation result shows the hybrid 2-level cache system optimized by our method reduces the energy consumption by 42% at the best case of an instruction memory subsystem without increasing the die area.