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Proceedings of Bipolar/Bicmos Circuits and Technology Meeting最新文献

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A double-spacer technology for the formation of very narrow emitter (0.3 /spl mu/m) double-polysilicon bipolar transistors using 0.8-/spl mu/m photolithography 采用0.8-/spl μ m光刻技术，形成极窄发射极(0.3 /spl μ m)双多晶硅双极晶体管的双间隔技术
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493875
C. Tsai, B. Scharf, P. Garone, P. Humphries, K. O
{"title":"A double-spacer technology for the formation of very narrow emitter (0.3 /spl mu/m) double-polysilicon bipolar transistors using 0.8-/spl mu/m photolithography","authors":"C. Tsai, B. Scharf, P. Garone, P. Humphries, K. O","doi":"10.1109/BIPOL.1995.493875","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493875","url":null,"abstract":"Emitter widths of 0.3 /spl mu/m on double-polysilicon bipolar transistors are achieved using 0.8-/spl mu/m photolithography and a double-spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f/sub T/ and f/sub max/.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"87 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131177135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Class-AB high-speed low-power op amp in BiCMOS technology 一种基于BiCMOS技术的ab类高速低功耗运放
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493857
S. Sen, B. Leung
{"title":"A Class-AB high-speed low-power op amp in BiCMOS technology","authors":"S. Sen, B. Leung","doi":"10.1109/BIPOL.1995.493857","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493857","url":null,"abstract":"A low-power, high-speed BiCMOS op amp is described. It uses a wideband, composite PMOS-vertical-NPN structure as a substitute for vertical-PNP transistors to realize a Class-AB input stage with very high small and large signal transconductances and op amp slew-rate.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131613865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry 具有30-ps 120 k逻辑门和片上测试电路的0.9 ns 1.15 mb ECL-CMOS SRAM
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493863
K. Higeta, M. Usami, M. Ohayashi, Y. Fujimura, Masahiko Nishiyama, S. Isomura, K. Yamaguchi, Y. Idei, H. Nambu, K. Ohhata, Nadateru Hanta
{"title":"A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry","authors":"K. Higeta, M. Usami, M. Ohayashi, Y. Fujimura, Masahiko Nishiyama, S. Isomura, K. Yamaguchi, Y. Idei, H. Nambu, K. Ohhata, Nadateru Hanta","doi":"10.1109/BIPOL.1995.493863","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493863","url":null,"abstract":"A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126121982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
12-GHz Gilbert mixers using a manufacturable Si/SiGe epitaxial-base bipolar technology 采用可制造的Si/SiGe外延基双极技术的12ghz Gilbert混频器
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493894
Jeffrey S. Glenn, Mary E. Case, David L. Harame, B. Meyerson, R. Poisson
{"title":"12-GHz Gilbert mixers using a manufacturable Si/SiGe epitaxial-base bipolar technology","authors":"Jeffrey S. Glenn, Mary E. Case, David L. Harame, B. Meyerson, R. Poisson","doi":"10.1109/BIPOL.1995.493894","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493894","url":null,"abstract":"We present Gilbert mixer circuits, fabricated with an epitaxial-base Si/SiGe bipolar technology, having bandwidths of up to 12 GHz and gain-bandwidth products in excess of 22 GHz.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125387943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
On log domain filtering for RF applications 关于射频应用的日志域滤波
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493856
D. Frey
{"title":"On log domain filtering for RF applications","authors":"D. Frey","doi":"10.1109/BIPOL.1995.493856","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493856","url":null,"abstract":"The design concept of log filters is reviewed. A new second order filter topology which is particularly useful for RF signal processing is introduced with a discussion of its features which meet the needs of RF design.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129365047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-speed insulated-gate bipolar transistors fabricated using silicon wafer bonding 采用硅片键合技术制造的高速绝缘栅双极晶体管
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493899
S. Tu, G. Tam, P. Tam, A. Taomoto
{"title":"High-speed insulated-gate bipolar transistors fabricated using silicon wafer bonding","authors":"S. Tu, G. Tam, P. Tam, A. Taomoto","doi":"10.1109/BIPOL.1995.493899","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493899","url":null,"abstract":"A high-speed IGBT fabricated using silicon direct wafer bonding is demonstrated. By controlling the heavily-doped n/sup +/ buffer layer in the device, an on-state voltage drop of 1.4 V at current density of 100 A/cm/sup 2/ and a turn-off fall time less than 100 nanoseconds are achieved.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130744862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The design and technology requirements of a 9-channel RS485 transceiver for ultra-SCSI applications 超scsi应用的9通道RS485收发器的设计和技术要求
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493886
M. Corsi, E. Suder, J. Tran, L. Hutter, J.P. Smith, L. Springer
{"title":"The design and technology requirements of a 9-channel RS485 transceiver for ultra-SCSI applications","authors":"M. Corsi, E. Suder, J. Tran, L. Hutter, J.P. Smith, L. Springer","doi":"10.1109/BIPOL.1995.493886","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493886","url":null,"abstract":"The design aspects of a 9-channel ultra-SCSI transceiver chip are discussed including improvements to speed, power consumption and die size over a previous generation chip, Discussion of the enabling linear BiCMOS technology and an ESD strategy, critical to the function of this class of chip, are presented. Finally, the results of prototype silicon are reviewed.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121810235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A universal 3.3 V 1 GHz BiCMOS transceiver (driver/receiver) 通用3.3 V 1 GHz BiCMOS收发器(驱动/接收)
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493878
M. Elrabaa, M. Elmasry, D. Malhi
{"title":"A universal 3.3 V 1 GHz BiCMOS transceiver (driver/receiver)","authors":"M. Elrabaa, M. Elmasry, D. Malhi","doi":"10.1109/BIPOL.1995.493878","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493878","url":null,"abstract":"A universal BiCMOS low-voltage-swing transceiver (driver/receiver) with low on-chip power consumption is reported. Operating at 3.3 V, it can drive/receive low-voltage-swing signals with termination voltages ranging from 5 V down to 2 V without using any external reference voltages.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116568064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A self-aligned SiGe base bipolar technology using cold wall UHV/CVD and its application to optical communication ICs 冷壁超高压/CVD自对准SiGe基极双极技术及其在光通信集成电路中的应用
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493872
F. Sato, T. Hashimoto, T. Tatsumi, M. Soda, H. Tezuka, T. Suzaki, T. Tashiro
{"title":"A self-aligned SiGe base bipolar technology using cold wall UHV/CVD and its application to optical communication ICs","authors":"F. Sato, T. Hashimoto, T. Tatsumi, M. Soda, H. Tezuka, T. Suzaki, T. Tashiro","doi":"10.1109/BIPOL.1995.493872","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493872","url":null,"abstract":"A self-aligned SiGe base bipolar technology and its application to optical communication ICs are presented. Using cold wall ultra-high vacuum (UHV)/CVD technology, a self-aligned selective SiGe/Si epitaxial growth can be realized for the overhanging structure of the base electrode polysilicon. This is a novel self-aligned bipolar transistor, which we call a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor. The maximum cut-off frequency f/sub T/ of 60 GHz and the maximum frequency of operation f/sub max/ of 50 GHz have been obtained. This technology has been applied to optical communication ICs. A receiver and a transmitter ICs fabricated on a silicon on insulator (SOI) substrate stably operate at up to 20 Gb/s.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125943710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
The optical terminal IC: A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip 光终端IC:一个2.4 Gb/s的接收器和一个1:16的解复用器
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493889
F. Sato, H. Tezuka, M. Soda, T. Hashimoto, T. Suzaki, T. Tatsumi, T. Morikawa, T. Tashiro
{"title":"The optical terminal IC: A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip","authors":"F. Sato, H. Tezuka, M. Soda, T. Hashimoto, T. Suzaki, T. Tatsumi, T. Morikawa, T. Tashiro","doi":"10.1109/BIPOL.1995.493889","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493889","url":null,"abstract":"This paper reports the 2.4 Gb/s optical terminal IC integrating high-speed analog and digital circuits for future optical networks. The IC consists of a receiver (a preamplifier, an automatic gain control (AGC) amplifier, a phase-locked-loop (PLL), a D-F/F), and a 1:16 demultiplexer (DMUX). An input offset control circuit is included in the AGC amplifier for wide dynamic range. The trench isolation and SOI technologies are introduced to reduce the crosstalk effect between the amplifiers and the PLL.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"61 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126125651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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