A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI:10.1109/BIPOL.1995.493863

K. Higeta, M. Usami, M. Ohayashi, Y. Fujimura, Masahiko Nishiyama, S. Isomura, K. Yamaguchi, Y. Idei, H. Nambu, K. Ohhata, Nadateru Hanta

引用次数: 11

Abstract

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.

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具有30-ps 120 k逻辑门和片上测试电路的0.9 ns 1.15 mb ECL-CMOS SRAM

开发了一种具有30-ps 120 k逻辑门的0.9 ns 1.15 mb ECL-CMOS SRAM。为了提供良好的可测试性、可靠性和稳定性，提出了片上测试电路、存储单元测试技术、高稳定电流源和软错误免疫存储单元。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of Bipolar/Bicmos Circuits and Technology Meeting

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