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Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)最新文献

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General design principles of self-testing code-disjoint PLAs 自测试代码分离pla的一般设计原则
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398819
S.J. Piestrak
{"title":"General design principles of self-testing code-disjoint PLAs","authors":"S.J. Piestrak","doi":"10.1109/ATS.1993.398819","DOIUrl":"https://doi.org/10.1109/ATS.1993.398819","url":null,"abstract":"This paper presents general principles of designing self-testing (ST) code-disjoint (CD) PLAs under fault model which covers three classes of typical PLA faults. It is assumed that both inputs and outputs of a PLA are encoded with an unordered code and that PLAs are inverter-free. It is shown that the necessary condition for ST and CD is that the input code of a PLA is closed. The formal conditions for the existence of a one- and multi-stage ST and CD PLA are formulated. The new PLA-based self-testing checkers for various closed unordered codes are less complex and/or faster than existing designs, and for some unordered codes they are the first ever proposed. An important property of all new designs is that they are all single crosspoint irredundant.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121911111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
T-BIST: A built-in self-test for analog circuits based on parameter translation T-BIST:基于参数转换的模拟电路内置自检
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398798
M. Slamani, B. Kaminska
{"title":"T-BIST: A built-in self-test for analog circuits based on parameter translation","authors":"M. Slamani, B. Kaminska","doi":"10.1109/ATS.1993.398798","DOIUrl":"https://doi.org/10.1109/ATS.1993.398798","url":null,"abstract":"In this paper we propose a technique for verifying whether or not the tested parameters are within the acceptance range. This technique called T-BIST is based on the conversion of each detected parameter to a DC voltage. The resulting DC voltage is proportional to the measured parameter and can be easily manipulated and tested. The test of the DC voltage value consists in comparing it to two reference voltages, V/sub refmin/ and V/sub refmax/, limiting the acceptance range of each parameter. The detection of the parameters and their conversion to a DC voltage is achieved by a detection and translation circuit incorporated in the circuit under test. An experimental study has been conducted to choose the translation relation of the parameters into DC voltages before designing the T-BIST structure. The sensitivity approach is used as the mathematical tool for this analysis.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125573823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Neural network realization of Markov model of TMR systems with compensating failures 带故障补偿的TMR系统马尔可夫模型的神经网络实现
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398777
Y. Zhou, Y. Min
{"title":"Neural network realization of Markov model of TMR systems with compensating failures","authors":"Y. Zhou, Y. Min","doi":"10.1109/ATS.1993.398777","DOIUrl":"https://doi.org/10.1109/ATS.1993.398777","url":null,"abstract":"Reliability synthesis as a reverse of reliability analysis has the same importance as reliability estimation. One important issue in reliability synthesis is to find failure rates and repair rates of units, given the desired reliability requirement. Compensation of failures can be very significant for fail-fast TMR systems. This paper presents a new model of TMR systems in which fail-fast rates and compensating failures are considered, and employs a forward neural network to compute the failure rates and repair rates that meet the desired reliability requirement and the preassumed fail-fast rates. The failure rates and repair rates are obtained after the neural network becomes stable. Simulation results show that the model presented in this paper can allow higher failure rates of units to achieve the same reliability than the classical model. So we can design a redundant digital system with a much lower cost.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126574799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automatic fault location using E-beam and LSI testers 自动故障定位使用电子束和LSI测试仪
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398814
N. Itazaki, T. Sumioka, S. Kajihara, K. Kinoshita
{"title":"Automatic fault location using E-beam and LSI testers","authors":"N. Itazaki, T. Sumioka, S. Kajihara, K. Kinoshita","doi":"10.1109/ATS.1993.398814","DOIUrl":"https://doi.org/10.1109/ATS.1993.398814","url":null,"abstract":"In this paper, we propose a method for locating faults using an E-beam tester together with a conventional LSI tester. This method applies the fault analysis method using vector pairs by Cox and Rajski to the analysis and diagnosis using E-beam tester. Since an accurate observation of VLSI is possible by E-beam probing, high fault coverage with a few observation time can be attained.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126593365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A C-testable DCVS GF(2/sup m/) multiplier 可c测试的DCVS GF(2/sup m/)乘法器
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398805
T. Chang, J.H.T. Chen, J. Hsu
{"title":"A C-testable DCVS GF(2/sup m/) multiplier","authors":"T. Chang, J.H.T. Chen, J. Hsu","doi":"10.1109/ATS.1993.398805","DOIUrl":"https://doi.org/10.1109/ATS.1993.398805","url":null,"abstract":"A C-testable design, which requires only five test patterns, for dynamic clocked differential cascode voltage switch (DCVS) GF(2/sup m/) multiplier circuit is proposed. The hardware overhead includes two extra control lines and m XOR gates. For simplicity, the area overhead in transistor counts is /sup 1//sub 3m+1/ for a GF(2/sup m/) multiplier.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132822149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Detection of multiple faults using SSFTS in CMOS logic circuits 用SSFTS检测CMOS逻辑电路中的多故障
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398817
C. Tong, D. Lu
{"title":"Detection of multiple faults using SSFTS in CMOS logic circuits","authors":"C. Tong, D. Lu","doi":"10.1109/ATS.1993.398817","DOIUrl":"https://doi.org/10.1109/ATS.1993.398817","url":null,"abstract":"With the increasing density of CMOS VLSI circuits, it is necessary to test for the combinations of different multiple faults. This paper studies the possibility of using single stuck-at fault test set (SSFTS) to detect multiple faults and their combinations. The paper shows that a single stuck-at fault test set can detect single and multiple self-feedback bridging faults, combinations of feedback bridging, input bridging and stuck-on faults when current monitoring is done. We also prove that a single stuck-at fault test set can detect the combination of single stuck-open fault and some other faults like bridging and stuck-on faults when both logic and current monitoring are done.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129483013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A current testing for CMOS static RAMs to reduce testing costs 当前测试CMOS静态ram，以降低测试成本
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398810
H. Yokoyama, H. Tamamoto, Y. Narita
{"title":"A current testing for CMOS static RAMs to reduce testing costs","authors":"H. Yokoyama, H. Tamamoto, Y. Narita","doi":"10.1109/ATS.1993.398810","DOIUrl":"https://doi.org/10.1109/ATS.1993.398810","url":null,"abstract":"This paper presents a methodology to reduce the testing costs of a CMOS static RAMs (SRAMs), based on a current testing. In this test method, the structure of SRAMs is modified so that all the cells can be driven simultaneously. A fault in the memory cell array can be detected by only observing the abnormal current. Since the whole cell array could be treated as if it were a single cell, the length of the test sequences is not dependent on the size of the memory cell array and must be very short.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127320335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A two-phase fault simulation scheme for sequential circuits 时序电路的两相故障仿真方案
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398780
Wen Ching Wu, Chung-Len Lee, Jwu-E Chen
{"title":"A two-phase fault simulation scheme for sequential circuits","authors":"Wen Ching Wu, Chung-Len Lee, Jwu-E Chen","doi":"10.1109/ATS.1993.398780","DOIUrl":"https://doi.org/10.1109/ATS.1993.398780","url":null,"abstract":"A two-phase fault simulation scheme for sequential circuits is proposed. The scheme is done by first performing the true value simulation with several initial patterns and then by performing the fault simulation with the rest of patterns. With the fault simulation approach, some faults which consume much simulation time can be easily and quickly identified and dropped early. As a result, significant speedup on simulation time is obtained. Five cases of faults which cause problems in fault simulation are also discussed.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124599288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Software upset analysis: A case study of the HS1602 microprocessor 软件故障分析:以HS1602微处理器为例
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398778
G. Choi, R. K. Iyer
{"title":"Software upset analysis: A case study of the HS1602 microprocessor","authors":"G. Choi, R. K. Iyer","doi":"10.1109/ATS.1993.398778","DOIUrl":"https://doi.org/10.1109/ATS.1993.398778","url":null,"abstract":"This paper describes a simulation based approach to quantify the impact of low-level transient errors at the software execution level. Automated analysis, for the run-time injection of transients at the device level and the assessment of the resulting impact on the program-control flow, is described. Using test workloads, the type of upsets at the program-flow level which can result from fault injection are determined. The methodology is illustrated by a case study of a microprocessor, used in the jet-engine controller of Boeing 747 and 757 aircrafts. For each section in the test program, the chance of having single and multiple upsets from the fault injection is determined. The analysis showed that about 20% of all upsets are multiple in nature. The result suggests that current methods of validation that assume single upsets may be inadequate.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"92 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128019544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MISSED: An environment for mixed-signal microsystem testing and diagnosis 错过:混合信号微系统测试和诊断的环境
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398785
H. Kerkhoff, G. Docherty
{"title":"MISSED: An environment for mixed-signal microsystem testing and diagnosis","authors":"H. Kerkhoff, G. Docherty","doi":"10.1109/ATS.1993.398785","DOIUrl":"https://doi.org/10.1109/ATS.1993.398785","url":null,"abstract":"A tight link between design and test data is proposed for speeding up test-pattern generation and diagnosis during mixed-signal prototype verification. Test requirements are already incorporated at the behavioral level and specified with increased detail at lower hierarchical levels. A strict distinction between generic routines and implementation data makes reuse of software possible. A testability-analysis tool and test and DFT libraries support the designer to guarantee testability. Hierarchical backtrace procedures in combination with an expert system and fault libraries assist the designer during mixed-signal chip debugging.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123577953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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