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Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)最新文献

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Parallel computation of LFSR signatures LFSR特征的并行计算
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398783
B. Narendran, M. Franklin, K. Saluja
{"title":"Parallel computation of LFSR signatures","authors":"B. Narendran, M. Franklin, K. Saluja","doi":"10.1109/ATS.1993.398783","DOIUrl":"https://doi.org/10.1109/ATS.1993.398783","url":null,"abstract":"Off-line determination of signatures (both good circuit and faulty circuits) for built-in self-test applications is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we present a parallel algorithm that can speed up the computation of (single input and multiple input) LFSR signatures by almost a factor of n, where n is the number of processors used. This parallel algorithm is designed by dividing that total number of time-frames to be simulated into partitions, and assigning each partition to a processor. Each processor determines the contribution of its partition to the final signature, and the contributions of different processors are merged, with very little effort, to obtain a single signature. The speedup given by our parallel algorithm is over and above any speedups provided by other sequential speedup techniques such as the use of lookup tables. We also present the results of a simulation study showing the speedup achieved by the parallel algorithm on a Sequent multiprocessor system.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133926090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Proof that Akers' algorithm for locally exhaustive testing gives minimum test sets of combinational circuits with up to four outputs 证明了局部穷举测试的Akers算法给出了最多四个输出的组合电路的最小测试集
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398773
H. Michinishi, T. Yokohira, T. Okamoto
{"title":"Proof that Akers' algorithm for locally exhaustive testing gives minimum test sets of combinational circuits with up to four outputs","authors":"H. Michinishi, T. Yokohira, T. Okamoto","doi":"10.1109/ATS.1993.398773","DOIUrl":"https://doi.org/10.1109/ATS.1993.398773","url":null,"abstract":"In this paper, we prove that Akers' test generation algorithm for the locally exhaustive testing gives a minimum test set (MLTS) for every combinational circuit (CUT) with up to four outputs. That is, we clarify that Akers' test pattern generator can generate an MLTS for such CUT.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131685137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A systematic method to classify scan cells 一种对扫描细胞进行分类的系统方法
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398808
K.-J. Lee, Ming-Hsuan Lu, J. Wang
{"title":"A systematic method to classify scan cells","authors":"K.-J. Lee, Ming-Hsuan Lu, J. Wang","doi":"10.1109/ATS.1993.398808","DOIUrl":"https://doi.org/10.1109/ATS.1993.398808","url":null,"abstract":"A scan cell (S-cell) is a basic storage unit for a scan-based sequential circuit. Depending on different requirements on the circuit under test, many design variations of S-cells exist. In this paper a systematic method to classify all practical S-cells is presented. Based on a novel graph representation and a set of design criteria, we find that all practical S-cells can be classified into 19 schematic structures which can be further divided into 66 different substructures. Among all of these substructures less than 10 have been previously identified and used.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122584989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Subjective fault evaluation method of electronic circuits 电子电路主观故障评价方法
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398786
M. Hashizume, Y. Iwata, T. Tamesada
{"title":"Subjective fault evaluation method of electronic circuits","authors":"M. Hashizume, Y. Iwata, T. Tamesada","doi":"10.1109/ATS.1993.398786","DOIUrl":"https://doi.org/10.1109/ATS.1993.398786","url":null,"abstract":"In this paper, fault evaluation problems, which are to determine whether electronic circuits are faulty or not, are discussed and a new fault evaluation method for electronic circuits, which is based on a fuzzy inference technique, is proposed. In our method, evaluation characteristics of an expert test engineer are defined by means of directed graphs. By using the graphs, fault evaluation results can be obtained, which are satisfied by the expert, even if a test engineer is novice. The effectiveness of our method is checked by some experiments of amplifier circuits.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130776184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The driver/receiver conflict problem in interconnect testing with boundary-scan 边界扫描互连测试中驱动/接收端冲突问题
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398806
L. Jin
{"title":"The driver/receiver conflict problem in interconnect testing with boundary-scan","authors":"L. Jin","doi":"10.1109/ATS.1993.398806","DOIUrl":"https://doi.org/10.1109/ATS.1993.398806","url":null,"abstract":"This paper explores the driver/receiver conflict problem in interconnect testing with bidirectional pins and 3-state output pins in boundary-scan. The objective is to have a higher-level (higher than chip) designer be aware of this conflict. Some existing algorithms are reviewed.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123641251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
LFSROM: A hardware test pattern generator for deterministic ISCAS85 test sets lfrom:用于确定性ISCAS85测试集的硬件测试模式生成器
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398796
C. Dufaza, C. Chevalier, L. L. Y. Lew Yan Voon
{"title":"LFSROM: A hardware test pattern generator for deterministic ISCAS85 test sets","authors":"C. Dufaza, C. Chevalier, L. L. Y. Lew Yan Voon","doi":"10.1109/ATS.1993.398796","DOIUrl":"https://doi.org/10.1109/ATS.1993.398796","url":null,"abstract":"Deterministic testing is by far the most interesting built-in self-test (BIST) technique because of the minimal number of test patterns required and of the known fault coverage. However, it is still not applicable since none of the existing deterministic test pattern generators (TPGs) is at the same time efficient and small. The LFSROM architecture which is presented herein is thus an attempt to solve the hardware cost problem without altering the initial test sequence in order to preserve the advantages of minimal sequence length of deterministic testing over pseudo-random and (pseudo)-exhaustive testing. The LFSROM concept is described and several implementations of test sets generated for the ISCAS85 benchmark circuits have been compared with those of equivalent ROM designs and the results reported in the form of curves and bar charts.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127480929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
On the eliminating of parameters /spl alpha/ and /spl beta/ in STAFAN STAFAN中/spl alpha/和/spl beta/参数的消除
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398782
J. Ding, J. Hu
{"title":"On the eliminating of parameters /spl alpha/ and /spl beta/ in STAFAN","authors":"J. Ding, J. Hu","doi":"10.1109/ATS.1993.398782","DOIUrl":"https://doi.org/10.1109/ATS.1993.398782","url":null,"abstract":"STAFAN algorithm (1985) is regarded as a good alternative to fault simulation of digital circuits. However, this algorithm has two parameters /spl alpha/ and /spl beta/ to be determined by fault simulation and so it is of no practical uses. This article analyzes the probability distribution of random signals at circuit nodes, and proves that controllability is in normal distribution. Thus the unbiasing estimate of fault detection probability can be obtained. Moreover, according to the concept of observability, we can eliminate parameter /spl beta/. For actual circuits the fault coverage obtained from the modified STAFAN agrees favorably with the fault simulation results.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"AES-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126496658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test generation for E-beam testing of VLSI circuits VLSI电路电子束测试的测试生成
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398787
O. Choy, L. Chan, R. Chan, C. Chan
{"title":"Test generation for E-beam testing of VLSI circuits","authors":"O. Choy, L. Chan, R. Chan, C. Chan","doi":"10.1109/ATS.1993.398787","DOIUrl":"https://doi.org/10.1109/ATS.1993.398787","url":null,"abstract":"With the increasing use of E-beam testing, chip test under highly observable condition has become increasing important. Using E-beam probing, the logical value of the internal signal lines running in the top-metal layer can be observed directly. The number of test vectors can be reduced by observing internal nodes. In this paper, we access a method to generate test vectors and corresponding internal nodes for single stuck-at faults in combinational circuits. This approach differs from the conventional methods which generates test vectors with a fixed number of observable points.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126509610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testing of parallel programs based on primitive dependence graph 基于原语依赖图的并行程序测试
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398791
H.-P. Wu
{"title":"Testing of parallel programs based on primitive dependence graph","authors":"H.-P. Wu","doi":"10.1109/ATS.1993.398791","DOIUrl":"https://doi.org/10.1109/ATS.1993.398791","url":null,"abstract":"Because of the nondeterministic timing ordering behavior of parallel primitives, testing of parallel programs is more difficult than that of serial programs. In this paper, we present a new testing strategy for parallel programs---static testing of parallel programs with their primitive dependence graphs. We have developed methods to analyze the timing ordering dependences between primitives and to construct primitive dependence graph. Approaches for static detecting errors with primitive dependence graph have also been discussed.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On properties and implementations of inverting ALSC for use in built-in self-testing 用于内建自检的反相ALSC的性质和实现
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398822
K. Furuya, P. Y. Koh, E. McCluskey
{"title":"On properties and implementations of inverting ALSC for use in built-in self-testing","authors":"K. Furuya, P. Y. Koh, E. McCluskey","doi":"10.1109/ATS.1993.398822","DOIUrl":"https://doi.org/10.1109/ATS.1993.398822","url":null,"abstract":"Clockwise inverting sequences of original pseudo-random ones are considered effective for two-pattern testing of CMOS circuits. This paper describes a class of circuits which can generate such sequences and conveniently referred as inverting ALSC (autonomous linear sequential circuit). The simulation results show that inverting ALSC generated sequences have strong dependency on the original cyclic structures and can be completely described using some linear recurrence relations. Relationships between original sequences and their inverting ones are illustrated to exhibit correspondence in terms of cycle sets. Then, the possibility of realizing inverting ALSC by simply inserting inverters between stages is discussed. It is further shown that there is no significant difference between two-pattern test capabilities in an original ALSC and the inverting one.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126250149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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