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Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)最新文献

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Design of efficient totally self-checking checkers for m-out-of-n code m- of-n代码的高效全自检检查器设计
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398818
W.-F. Chang, C.-W. Wu
{"title":"Design of efficient totally self-checking checkers for m-out-of-n code","authors":"W.-F. Chang, C.-W. Wu","doi":"10.1109/ATS.1993.398818","DOIUrl":"https://doi.org/10.1109/ATS.1993.398818","url":null,"abstract":"This paper presents a new design method of efficient totally self-checking (TSC) checkers for m-out-of-n code. The design procedure has three steps. First, we append an appropriate number of 1's to the m/n code to get a k/2k code, and design a TSC checker for this k/2k code which can be easily constructed by the conventional method. Then, we delete the appended 1's and simplify the circuit to get an m/n code checker. Finally, we modify the checker using super gates to meet the self-testing conditions ad get a final TSC m/n code checker. Compared with previous methods, our TSC checker requires significantly less hardware.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123405089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An optimal scheme of parallel processing for test generation in a distributed system 分布式系统测试生成并行处理的优化方案
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398772
T. Inoue, T. Yonezawa, H. Fujiwara
{"title":"An optimal scheme of parallel processing for test generation in a distributed system","authors":"T. Inoue, T. Yonezawa, H. Fujiwara","doi":"10.1109/ATS.1993.398772","DOIUrl":"https://doi.org/10.1109/ATS.1993.398772","url":null,"abstract":"This paper presents an approach to parallel processing of test generation for logic circuits in a loosely-coupled distributed network of general purpose computers. We first analyze the relation between the number of processors and the total processing time for a client-server model (CS model). The result of the analysis shows that for the CS model there exists an optimal number of processors which minimizes the total processing time. In order to get a more efficient scheme than the CS model, we propose another model called a client-agent-server model (CAS model), which is derived by adding agent processors to the CS model. We formulate the problem of test generation on the CAS model, and analyze the relation between the number of processors and the total processing time. Our analysis leads to an optimal scheme for the CAS model which minimizes the total processing time for a given number of processors. We present experimental results for the ISCAS benchmark circuits by implementing the CAS model on a network of workstations.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121540401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bayesian inference for fault diagnosis in real-time distributed systems 实时分布式系统故障诊断中的贝叶斯推理
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398827
Y.L.C. Chang, L. Lander, Horng-Shing Lu, M. T. Wells
{"title":"Bayesian inference for fault diagnosis in real-time distributed systems","authors":"Y.L.C. Chang, L. Lander, Horng-Shing Lu, M. T. Wells","doi":"10.1109/ATS.1993.398827","DOIUrl":"https://doi.org/10.1109/ATS.1993.398827","url":null,"abstract":"We propose fault location strategies based on a Bayesian decision-theoretic approach. The proposed B-algorithm can locate the failed units in a distributed system with complexity which is linear in the number of subsystems in the network, making it suitable for hard real-time applications. The method is probabilistic and comparison-based, employing multiple incomplete test concepts.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129966722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Error localization in test outputs: A generalized analysis of signature compression 测试输出中的错误定位:签名压缩的广义分析
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398824
S. Demidenko, V. Piuri, A. Ivaniukovich
{"title":"Error localization in test outputs: A generalized analysis of signature compression","authors":"S. Demidenko, V. Piuri, A. Ivaniukovich","doi":"10.1109/ATS.1993.398824","DOIUrl":"https://doi.org/10.1109/ATS.1993.398824","url":null,"abstract":"Signature compression is widely used to reduce the volume of information generated by testing. Localization of the faulty component in the system under test, starting from the signature analysis, may be a complex problem related to identification of the erroneous bits in the sequence being compressed and to the error model of the system. A first technique for low-multiplicity errors is based on error effects' superposition. A novel general solution is derived for any-multiplicity errors from the analytical description of signature compression.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134059304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimization of deterministic test sets using an estimation of product quality 使用产品质量估计的确定性测试集的优化
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398790
G. Spiegel, A. P. Stroele
{"title":"Optimization of deterministic test sets using an estimation of product quality","authors":"G. Spiegel, A. P. Stroele","doi":"10.1109/ATS.1993.398790","DOIUrl":"https://doi.org/10.1109/ATS.1993.398790","url":null,"abstract":"The probabilities of faults in VLSI circuits generally differ by order of magnitude. This paper presents an approach to product quality estimation that considers these different fault probabilities. Two efficient algorithms are described that optimize deterministic test sets such that a high product quality is achieved with short test lengths.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114896805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An approach to large program testing with tool WHEN 一种使用WHEN工具进行大型程序测试的方法
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398792
Huaiyu Zhu, F. Chen
{"title":"An approach to large program testing with tool WHEN","authors":"Huaiyu Zhu, F. Chen","doi":"10.1109/ATS.1993.398792","DOIUrl":"https://doi.org/10.1109/ATS.1993.398792","url":null,"abstract":"The problem to test large application and system programs efficiently in supercomputer systems is discussed. Many difficulties exist when large programs are concerned. In order to overcome some of these difficulties, we design a novel software tool named WHEN, which has been used to solve some dynamic internal testing problems, such as flexible flowtracing, debugging of deep rooted errors or faults, internal structural analysis of foreign programs, program testing in batch and real time systems, etc. in the supercomputer software development where large programs are often found. This paper first discusses some problems in the large program testing. Then WHEN is introduced with an efficient implementation of WHEN on supercomputers. Third, an approach to large program testing with the tool WHEN is explained with a few practical application examples. Finally, a method to improvement of software design for testability and maintainability is suggested.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129741010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testing scheduling and control in a parallel processing environment 在并行处理环境中测试调度和控制
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398815
Xiang Dong
{"title":"Testing scheduling and control in a parallel processing environment","authors":"Xiang Dong","doi":"10.1109/ATS.1993.398815","DOIUrl":"https://doi.org/10.1109/ATS.1993.398815","url":null,"abstract":"In this paper, the testing scheduling problem based on circuit partitioning is formulated into index coloring of the parallel testing graph (PTG). It is known that the index coloring problem is exponential in time cost, but the testing scheduling problem is proved to be polynomially solvable in theory. According to this result, an optimal testing scheduling algorithm is offered in quadratic time. Finally, a control scheme during testing scheduling is presented, which minimizes the number of the extra control inputs of the multiplexors to 2.1n ICN, here ICN is the index chromatic number of the PTG.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116272592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Limitations of built-in current sensors (BICS) for I/sub DDQ/ testing 用于I/sub DDQ/测试的内置电流传感器(BICS)的局限性
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398812
S. Menon, Y. Malaiya, A. Jayasumana, C. Tong
{"title":"Limitations of built-in current sensors (BICS) for I/sub DDQ/ testing","authors":"S. Menon, Y. Malaiya, A. Jayasumana, C. Tong","doi":"10.1109/ATS.1993.398812","DOIUrl":"https://doi.org/10.1109/ATS.1993.398812","url":null,"abstract":"Quiescent current (I/sub DDQ/) drawn by a static CMOS device is extremely small and is of the order of nanoamperes. Under many faults, (I/sub DDQ/) can increase by several orders of magnitude. Either an external or an on-chip current sensor can be used to detect enhanced static current drawn by a static CMOS device. An on-chip sensor, termed a BICS (Built-In Current Sensor) can be significantly faster. Implementation of BICS has received a lot of interest in the recent years. Some limitations posed by BICS on I/sub DDQ/ measurement caused due to increase in I/sub DDQ/ settling time as well as propagation delay is considered. Results indicate that careful attention needs to be given to circuit partitioning for implementing BICS. Some of the considerations that need to be taken into account while designing new BICS are presented.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121043398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Reliable fail-safe systems 可靠的故障安全系统
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398775
M. Lubaszewski, B. Courtois
{"title":"Reliable fail-safe systems","authors":"M. Lubaszewski, B. Courtois","doi":"10.1109/ATS.1993.398775","DOIUrl":"https://doi.org/10.1109/ATS.1993.398775","url":null,"abstract":"A fault-tolerant scheme is presented which is based on two copies of a self-checking module and a fail-safe interface. The interface preserves the modules' safety and becomes fault-tolerant by embedding appropriate self-testing capabilities. We show that, for self-checking module area overheads not exceeding the theoretical upper bound of /spl radic/3-1 (73%), our fault-tolerant scheme is more reliable than the triplicated modular redundant structure.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131398870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Additive cellular automata as an on-chip test pattern generator 加性元胞自动机作为片上测试模式发生器
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398797
Sukumar Nandi, P. Chaudhuri
{"title":"Additive cellular automata as an on-chip test pattern generator","authors":"Sukumar Nandi, P. Chaudhuri","doi":"10.1109/ATS.1993.398797","DOIUrl":"https://doi.org/10.1109/ATS.1993.398797","url":null,"abstract":"Cellular Automata (CA) has been already proposed for generation of pseudo-random, pseudo-exhaustive and two-pattern test vectors. In the present work, a new concept of intermediate boundary CA has been projected that circumvents the problems associated with the generation of pseudo-random patterns using null and periodic boundary CA. Generation of an arbitrary set of deterministic test patterns for combinational logic is next investigated. Evaluating the given pattern set as a pseudo-noise (PN) sequence, a CA can be identified that generates the pattern set with minimal overhead. The best possible CA is picked up based on the analytical study of phaseshift analysis of various CA stages. Experimental results establishes this scheme as the desirable alternative to the conventional 'store and generate' schemes.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"397 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124687394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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