{"title":"使用产品质量估计的确定性测试集的优化","authors":"G. Spiegel, A. P. Stroele","doi":"10.1109/ATS.1993.398790","DOIUrl":null,"url":null,"abstract":"The probabilities of faults in VLSI circuits generally differ by order of magnitude. This paper presents an approach to product quality estimation that considers these different fault probabilities. Two efficient algorithms are described that optimize deterministic test sets such that a high product quality is achieved with short test lengths.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Optimization of deterministic test sets using an estimation of product quality\",\"authors\":\"G. Spiegel, A. P. Stroele\",\"doi\":\"10.1109/ATS.1993.398790\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The probabilities of faults in VLSI circuits generally differ by order of magnitude. This paper presents an approach to product quality estimation that considers these different fault probabilities. Two efficient algorithms are described that optimize deterministic test sets such that a high product quality is achieved with short test lengths.<<ETX>>\",\"PeriodicalId\":228291,\"journal\":{\"name\":\"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-11-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1993.398790\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1993.398790","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimization of deterministic test sets using an estimation of product quality
The probabilities of faults in VLSI circuits generally differ by order of magnitude. This paper presents an approach to product quality estimation that considers these different fault probabilities. Two efficient algorithms are described that optimize deterministic test sets such that a high product quality is achieved with short test lengths.<>