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Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)最新文献

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Fault modelisation of external shorts in CMOS circuits CMOS电路外部短路的故障建模
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398811
M. Renovell, P. Huc, Y. Bertrand
{"title":"Fault modelisation of external shorts in CMOS circuits","authors":"M. Renovell, P. Huc, Y. Bertrand","doi":"10.1109/ATS.1993.398811","DOIUrl":"https://doi.org/10.1109/ATS.1993.398811","url":null,"abstract":"As the density of VLSI CMOS circuits increases, external shorts are expected to become a very important failure. This paper analyzes the electrical behavior of static CMOS gates with external shorts. The fault modelization of such shorts is then considered in the context of functional testing. It is demonstrated that the detectability of a short with respect to functional testing depends on the short resistance value Rsh. When the fault is detectable, it is also demonstrated that 8 different logical models are necessary showing that the wired-Or and wired-AND models, classically used for test pattern generation, fault simulation and defect coverage evaluation are not sufficient. A theoretical electrical model of the shorted line potentials is defined. This realistic model takes into account the topological and technological parameters (W, L...) of the transistors. A global procedure is proposed including different steps: layout extraction, fault parameters extraction, automatic fault model affectation.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117343351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A distributed message routing algorithm for fault-tolerant hypercube systems 一种容错超立方体系统的分布式消息路由算法
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398779
Y. Min, Y. Min
{"title":"A distributed message routing algorithm for fault-tolerant hypercube systems","authors":"Y. Min, Y. Min","doi":"10.1109/ATS.1993.398779","DOIUrl":"https://doi.org/10.1109/ATS.1993.398779","url":null,"abstract":"A distributed message routing algorithm for faulty hypercube systems is described. To improve the efficiency, the algorithm adopts a heuristic backtracking strategy and each node provides an array to record its all neighbors faulty link information to avoid unnecessary searching for the known faulty links. Furthermore, the faulty link information is dynamically accumulated and the technique of heuristically searching for optimal link is used. The algorithm routes messages through the minimum feasible path between the sender and receiver if at least one such path exists, and takes the optimal path with higher probability when many faulty links exist in the faulty hypercube.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123849862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An algorithm for test generation of combinational circuits - research and implementation for critical path tracing 组合电路测试生成算法——关键路径跟踪的研究与实现
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398774
S. Yin, D. Wei
{"title":"An algorithm for test generation of combinational circuits - research and implementation for critical path tracing","authors":"S. Yin, D. Wei","doi":"10.1109/ATS.1993.398774","DOIUrl":"https://doi.org/10.1109/ATS.1993.398774","url":null,"abstract":"An algorithm for test pattern generation of combinational logic circuits - critical path tracing is presented in this paper. Differing from other fault oriented test generation algorithms, this algorithm is circuit oriented and generates test pattern from primary outputs towards primary inputs in a circuit. In addition, it does not need fault simulation, i.e., when a test pattern is obtained all the faults detected by this test pattern can be determined simultaneously. Some fundamental conceptions, detailed description of this algorithm are given in this paper. This algorithm has been implemented at a SUN workstation using C language, and some experimental results are offered.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131173951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of monitored self-checking sequential circuits for enhanced fault models 增强故障模型的监控自检顺序电路设计
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398821
R. Parekhji, G. Venkatesh, S. Sherlekar
{"title":"Design of monitored self-checking sequential circuits for enhanced fault models","authors":"R. Parekhji, G. Venkatesh, S. Sherlekar","doi":"10.1109/ATS.1993.398821","DOIUrl":"https://doi.org/10.1109/ATS.1993.398821","url":null,"abstract":"This paper discusses the design of monitored self-checking sequential circuits for the detection of single and multiple unidirectional stuck-at faults, as well as delay faults. It is shown how the monitoring machine approach provides a uniform error detection mechanism for the detection of these faults. Designs based on this method are shown to compare favourably, in terms of hardware overheads and fault coverage, with previous self-checking implementations based on restricted fault models.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Test set partitioning and dynamic fault dictionaries for sequential circuits 时序电路的测试集分区和动态故障字典
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398799
P. Ryan, W. Fuchs
{"title":"Test set partitioning and dynamic fault dictionaries for sequential circuits","authors":"P. Ryan, W. Fuchs","doi":"10.1109/ATS.1993.398799","DOIUrl":"https://doi.org/10.1109/ATS.1993.398799","url":null,"abstract":"This paper describes techniques for partitioning test sets and maintaining diagnostic information in partition dictionaries that are appropriate for efficient dynamic fault location. The partitioned test sets and partition dictionary produce a small list of candidate faults, which are further distinguished by a dynamic fault dictionary, created at the time of diagnosis. The dictionaries used are significantly smaller than full dictionaries and are computationally efficient. The approach is shown to be effective on sequential benchmark circuits.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123763448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
GID-testable two-dimensional sequential arrays for self-testing 用于自我测试的栅格可测试的二维顺序阵列
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398809
W. Huang, F. Lombardi, M. Lu
{"title":"GID-testable two-dimensional sequential arrays for self-testing","authors":"W. Huang, F. Lombardi, M. Lu","doi":"10.1109/ATS.1993.398809","DOIUrl":"https://doi.org/10.1109/ATS.1993.398809","url":null,"abstract":"This paper presents an approach for easily testable two-dimensional sequential arrays. This approach is an extension of GID (Group Identical and Different)-testability of combinational arrays in our previous work. In a GID-testable two-dimensional array, the primary x and y outputs are organized into groups and every group has more than one output. GID-testability not only ensures that identical test responses can be obtained from every output in the same group when the array is fault free, but it also ensures at least one output has different test responses from other outputs in a group when a cell in the array is faulty. Therefore, all faults can be detected under the assumption of a single faulty cell model. It is proved that an arbitrary two-dimensional sequential array is GID-testable if seven x-states and seven y-states are added to the original flow table of the basic cell of the array.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129805380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of fault propagation using fault injection in the UNIX system UNIX系统中基于故障注入的故障传播研究
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398776
W. Kao, D. Tang, R. K. Iyer
{"title":"Study of fault propagation using fault injection in the UNIX system","authors":"W. Kao, D. Tang, R. K. Iyer","doi":"10.1109/ATS.1993.398776","DOIUrl":"https://doi.org/10.1109/ATS.1993.398776","url":null,"abstract":"This paper presents a fault propagation study for the UNIX operating system (Sun OS 4.1.2). Both hardware and software faults are injected in the UNIX kernel by using FINE - a fault injection and monitoring environment - to investigate the propagation of various types of faults. Based on the experimental results, fault propagation models are built and transient reward analysis is performed to evaluate the performance loss due to a fault. Results from the experiments provide insight into the vulnerable aspects of the system where the fault tolerance techniques could be used.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130743646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The complexity of determining the sequential diagnosability number in the Malek's comparison model 在Malek比较模型中确定顺序可诊断性数的复杂性
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398801
Zhou Liuding, Y. Xiaofan, Chen Tinghuai, Tang Chen-li
{"title":"The complexity of determining the sequential diagnosability number in the Malek's comparison model","authors":"Zhou Liuding, Y. Xiaofan, Chen Tinghuai, Tang Chen-li","doi":"10.1109/ATS.1993.398801","DOIUrl":"https://doi.org/10.1109/ATS.1993.398801","url":null,"abstract":"The problem of determining the sequential diagnosability number of a system in the Malek's comparison model is an important one. In this paper, we show that the decision version of this problem is co-NP complete for general systems, and we present an O(|E| |V|/sup 3/2/ log /sub 2/(|V|)) algorithm for determining the sequential diagnosability number for a class of systems corresponding to bipartite graphs.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"32 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133425460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An approach to the analysis of the current testability of IC analog sections 一种分析IC模拟部分电流可测试性的方法
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398784
D. Mateo, M. Roca, F. Serra-Graells, A. Rubio
{"title":"An approach to the analysis of the current testability of IC analog sections","authors":"D. Mateo, M. Roca, F. Serra-Graells, A. Rubio","doi":"10.1109/ATS.1993.398784","DOIUrl":"https://doi.org/10.1109/ATS.1993.398784","url":null,"abstract":"Integrated circuits considering mixed analog and digital section parts are becoming a strategic target of the microelectronic design methodologies. Focussing our attention on the testing aspect and knowing the interest and efficiency of current testing in digital circuits the possibility to extend this technique to analog parts is analyzed in this work. An analysis of the behavior of typical analog blocks under exhaustive set of open and bridging defects shows the interest to consider quiescent power supply current as an additional observable for analog testing. A new sensor is presented and analyzed showing interesting self-testable features, the sensor (built-in sensor) is applied to an operational amplifier. The strategy is applied later to a mixed signal A/D flash converter where current testing is used for both digital and analog parts. The work presents for all the points considered results of experimentation from implemented ICs.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115639307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A new method for system diagnosis 一种新的系统诊断方法
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398794
S. Xu, J. Gao
{"title":"A new method for system diagnosis","authors":"S. Xu, J. Gao","doi":"10.1109/ATS.1993.398794","DOIUrl":"https://doi.org/10.1109/ATS.1993.398794","url":null,"abstract":"With the advent of parallel computing systems, the fault diagnosis of such systems becomes increasingly challenging and critical. In this paper, we first introduce the concept of binary decision diagram (BDD), based on which we present an efficient way to locate the faulty units according to what we call fault symptom (FS). The new technique is then proved to be optimal (shortest) in time-consuming. Finally, an intelligent searching procedure for fault diagnosis is given.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126318128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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