Fault modelisation of external shorts in CMOS circuits

Abstract

As the density of VLSI CMOS circuits increases, external shorts are expected to become a very important failure. This paper analyzes the electrical behavior of static CMOS gates with external shorts. The fault modelization of such shorts is then considered in the context of functional testing. It is demonstrated that the detectability of a short with respect to functional testing depends on the short resistance value Rsh. When the fault is detectable, it is also demonstrated that 8 different logical models are necessary showing that the wired-Or and wired-AND models, classically used for test pattern generation, fault simulation and defect coverage evaluation are not sufficient. A theoretical electrical model of the shorted line potentials is defined. This realistic model takes into account the topological and technological parameters (W, L...) of the transistors. A global procedure is proposed including different steps: layout extraction, fault parameters extraction, automatic fault model affectation.<>