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Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)最新文献

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Achieving minimal hardware multiple signature analysis for BIST 实现最小的BIST硬件多重签名分析
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398823
Y. Wu, A. Ivanov
{"title":"Achieving minimal hardware multiple signature analysis for BIST","authors":"Y. Wu, A. Ivanov","doi":"10.1109/ATS.1993.398823","DOIUrl":"https://doi.org/10.1109/ATS.1993.398823","url":null,"abstract":"This paper proposes a new method for achieving minimal hardware multiple intermediate signature analysis whereby n signatures are checked against a single reference. With a single reference, checking multiple signatures requires the same amount of hardware as for checking only one. However, checking multiple signatures has many advantages. In comparison to the method described by Y. Wie and A Ivahou (1993) in [13], the proposed method is faster by a factor of 2/sup k/, where k is the signature size. E.g., to check two 16-bit signatures against a single reference, the total CPU time cost (Sun Sparcstation 2) is less than 4 sec. for a test length of up to 2/sup 20/, independently of the size of the circuit under test (CUT).<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114328160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the testability of cascaded Reed Muller circuits 级联Reed Muller电路的可测试性
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398816
G. Lee, M. Hwang, M. J. Irwin, R. Owens
{"title":"On the testability of cascaded Reed Muller circuits","authors":"G. Lee, M. Hwang, M. J. Irwin, R. Owens","doi":"10.1109/ATS.1993.398816","DOIUrl":"https://doi.org/10.1109/ATS.1993.398816","url":null,"abstract":"One of the advantages of using Reed Muller representations to design logic circuits is known as the high testability of the realized circuits. However, there is little known about the testability of any type of multi-level Reed Muller circuits. In this paper, we analyze the testability of a class of multi-level Reed Muller circuits which are generated by the synthesis tool FACTOR. FACTOR uses matrix transformations using [bit-AND, bit-XOR] operators recursively to partition the circuit into smaller subcircuits, resulting in a class of hierarchial logic circuits composed of only AND and XOR gates. For the analysis of testability in these circuits, the necessary and sufficient condition for two-level Reed Muller circuits to be irredundant is given. Then, it is shown that any fault occurring in a node of the circuit, or the corresponding two-level Reed Muller circuit, can be propagated to the Primary Output of the circuit, satisfying 100% testability using single stuck-at fault model. This result is important because the high testability of multi-level Reed Muller circuits is demonstrated with a class of circuits which are generated by a currently available synthesis tool. A simple test generation algorithm developed with the testability analysis shows the effectiveness of test generation together with the verification of irredundancy in these circuits.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115882047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A pragmatic test pattern generation system for scan-designed circuits with logic value constraints 具有逻辑值约束的扫描设计电路的实用测试模式生成系统
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398771
E. Park
{"title":"A pragmatic test pattern generation system for scan-designed circuits with logic value constraints","authors":"E. Park","doi":"10.1109/ATS.1993.398771","DOIUrl":"https://doi.org/10.1109/ATS.1993.398771","url":null,"abstract":"In testing for practical logic circuits, there may exist logic value constraints on some part of logic circuits owing to various requirements on design and test. The inefficiency in handling the logic value constraints during the line justification stage of test generation may result in low fault coverage as well as excessive computer time with numerous fruitless searches. This paper presents a logic value system called taboo logic value to represent the logic value constraints and to identify additional logic value constraints using a taboo logic calculus. Also, a test pattern generation algorithm is discussed to show how the taboo logic system can be incorporated into existing test generation algorithms. Finally, experimental results demonstrate the efficiency of the taboo logic values.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114732110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PLANE: A new ATPG system for PLAs PLANE:一种新的pla ATPG系统
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398788
J.-D. Huang, W. Shen
{"title":"PLANE: A new ATPG system for PLAs","authors":"J.-D. Huang, W. Shen","doi":"10.1109/ATS.1993.398788","DOIUrl":"https://doi.org/10.1109/ATS.1993.398788","url":null,"abstract":"In this paper, a new PLA ATPG system PLANE is presented. PLANE uses the depth-first sharp operation for efficient test generation. Besides, a powerful test compaction technique using the intersection buffer is applied to get a more compact test set. PLANE also uses parallel fault simulation and backend fault simulation to exploit its performance. Experimental results show that the test length of PLANE is 7.5% shorter than that of PLATYPUS.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"633 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123957034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
FASSAD: Fault simulation with sensitivities and depth-first propagation FASSAD:基于灵敏度和深度优先传播的故障模拟
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398781
P.R. Sureshkumar, J. Jacob, M. Srinivas, V. Agrawal
{"title":"FASSAD: Fault simulation with sensitivities and depth-first propagation","authors":"P.R. Sureshkumar, J. Jacob, M. Srinivas, V. Agrawal","doi":"10.1109/ATS.1993.398781","DOIUrl":"https://doi.org/10.1109/ATS.1993.398781","url":null,"abstract":"We use depth-first propagation of fault effects to quickly terminate the simulation of detected faults. Using the true logic states of signals, gates are classified as either definitely sensitive or potentially sensitive. Based upon this classification, we formulate rules for efficient propagation of faulty circuit events. These techniques are implemented in a single fault propagation (SFP) program. Results on benchmark circuits demonstrate that the depth-first propagation requires smaller number of gate evaluations compared to the conventional breadth-first propagation. Our technique takes smaller CPU time compared to a concurrent fault simulator for the ISCAS85 benchmarks and a differential parallel fault simulator for some of the ISCAS89 sequential benchmarks.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121872183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimal interconnect diagnosis 最佳互连诊断
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398802
W. Shi, W. Fuchs
{"title":"Optimal interconnect diagnosis","authors":"W. Shi, W. Fuchs","doi":"10.1109/ATS.1993.398802","DOIUrl":"https://doi.org/10.1109/ATS.1993.398802","url":null,"abstract":"Interconnect diagnosis is an important problem in very large scale integration (VLSI), multi-chip module (MCM) and printed circuit board (PCB) production. The problem is to detect and locate all the shorts among a given set of nets using the minimum number of tests. In this paper, we prove matching lower bounds for two non-adaptive diagnosis problems, and give an optimal algorithm for the adaptive diagnosis problem. Our results provide optimal solutions to several open problems in interconnect diagnosis.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126177518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and implementation of a JTAG boundary-scan interface controller JTAG边界扫描接口控制器的设计与实现
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398807
Shen Xu Baang, Liang Hai
{"title":"Design and implementation of a JTAG boundary-scan interface controller","authors":"Shen Xu Baang, Liang Hai","doi":"10.1109/ATS.1993.398807","DOIUrl":"https://doi.org/10.1109/ATS.1993.398807","url":null,"abstract":"In this paper we present an architecture for JTAG boundary-scan interface controller which we have implemented as a basic RISC microprocessor chip. We also present a JTAG test language which makes the interface between machine and users very friendly.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134457668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multiple stuck-at fault diagnosis in combinational circuits based on restricted single sensitized paths 基于受限单敏化路径的组合电路多卡滞故障诊断
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398800
Hiroshi Takahashi, N. Yanagida, Y. Takamatsu
{"title":"Multiple stuck-at fault diagnosis in combinational circuits based on restricted single sensitized paths","authors":"Hiroshi Takahashi, N. Yanagida, Y. Takamatsu","doi":"10.1109/ATS.1993.398800","DOIUrl":"https://doi.org/10.1109/ATS.1993.398800","url":null,"abstract":"We describe a method for multiple stuck-at fault diagnosis in combinational circuits based on restricted single sensitized paths generated by a seven-valued calculus. Our method determines the set of all possible stuck-at faults from the faulty response observed at the primary output, based on deducing internal values along the sensitized path. By using the fault-free response observed at the primary output, we remove fault-free lines along the sensitized path from the set of the candidates, by checking whether the fault-free response is prevented by the candidate fault from propagating to the primary output regardless of the presence of any other candidates. Experimental results on the benchmark circuits show that the fault locations are identified within 2-25% of all stuck-at 0 and 1 faults on all lines in the circuit with up to fourfold multiple faults without probing internal lines.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132417547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
State encoding and functional decomposition for self-checking sequential circuit design 自检顺序电路的状态编码与功能分解设计
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398820
S. Pagey, S. Sherlekar, G. Venkatesh
{"title":"State encoding and functional decomposition for self-checking sequential circuit design","authors":"S. Pagey, S. Sherlekar, G. Venkatesh","doi":"10.1109/ATS.1993.398820","DOIUrl":"https://doi.org/10.1109/ATS.1993.398820","url":null,"abstract":"In a previous paper, we presented a functional decomposition technique for low cost self-checking realizations of combinational circuits. This technique can be applied directly to the design of the next state logic of FSMs. In this paper, we present a methodology for good state encoding which results in a low cost self-checking realization of the FSM. The state encoding problem for self-checking realizations of FSMs consists of (a) the choice of a code space for state encoding, and (b) the assignment of codewords to individual states. While (b) can be solved using existing state assignment tools, (a) is addressed for the first time in this paper.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123409871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A global BIST methodology 一个全球性的BIST方法论
Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI: 10.1109/ATS.1993.398795
T. Gheewala, H. Sucar, P. Varma
{"title":"A global BIST methodology","authors":"T. Gheewala, H. Sucar, P. Varma","doi":"10.1109/ATS.1993.398795","DOIUrl":"https://doi.org/10.1109/ATS.1993.398795","url":null,"abstract":"This paper presents a BIST methodology for CMOS gate-arrays. This BIST method involves the extension of a design-independent embedded grid-based test technology that is provided in the base of the gate array to provide an automatic and complete self-test. The use of globally shared test electronics minimizes the area overhead required, while the massive observability of internal circuit nodes afforded by an embedded grid allows high fault coverage of both stuck-at and manufacturing defects, such as shorts and opens, to be achieved.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123229211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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