{"title":"PLANE:一种新的pla ATPG系统","authors":"J.-D. Huang, W. Shen","doi":"10.1109/ATS.1993.398788","DOIUrl":null,"url":null,"abstract":"In this paper, a new PLA ATPG system PLANE is presented. PLANE uses the depth-first sharp operation for efficient test generation. Besides, a powerful test compaction technique using the intersection buffer is applied to get a more compact test set. PLANE also uses parallel fault simulation and backend fault simulation to exploit its performance. Experimental results show that the test length of PLANE is 7.5% shorter than that of PLATYPUS.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"633 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"PLANE: A new ATPG system for PLAs\",\"authors\":\"J.-D. Huang, W. Shen\",\"doi\":\"10.1109/ATS.1993.398788\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a new PLA ATPG system PLANE is presented. PLANE uses the depth-first sharp operation for efficient test generation. Besides, a powerful test compaction technique using the intersection buffer is applied to get a more compact test set. PLANE also uses parallel fault simulation and backend fault simulation to exploit its performance. Experimental results show that the test length of PLANE is 7.5% shorter than that of PLATYPUS.<<ETX>>\",\"PeriodicalId\":228291,\"journal\":{\"name\":\"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)\",\"volume\":\"633 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-11-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1993.398788\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1993.398788","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, a new PLA ATPG system PLANE is presented. PLANE uses the depth-first sharp operation for efficient test generation. Besides, a powerful test compaction technique using the intersection buffer is applied to get a more compact test set. PLANE also uses parallel fault simulation and backend fault simulation to exploit its performance. Experimental results show that the test length of PLANE is 7.5% shorter than that of PLATYPUS.<>