On the testability of cascaded Reed Muller circuits

Abstract

One of the advantages of using Reed Muller representations to design logic circuits is known as the high testability of the realized circuits. However, there is little known about the testability of any type of multi-level Reed Muller circuits. In this paper, we analyze the testability of a class of multi-level Reed Muller circuits which are generated by the synthesis tool FACTOR. FACTOR uses matrix transformations using [bit-AND, bit-XOR] operators recursively to partition the circuit into smaller subcircuits, resulting in a class of hierarchial logic circuits composed of only AND and XOR gates. For the analysis of testability in these circuits, the necessary and sufficient condition for two-level Reed Muller circuits to be irredundant is given. Then, it is shown that any fault occurring in a node of the circuit, or the corresponding two-level Reed Muller circuit, can be propagated to the Primary Output of the circuit, satisfying 100% testability using single stuck-at fault model. This result is important because the high testability of multi-level Reed Muller circuits is demonstrated with a class of circuits which are generated by a currently available synthesis tool. A simple test generation algorithm developed with the testability analysis shows the effectiveness of test generation together with the verification of irredundancy in these circuits.<>