{"title":"自检顺序电路的状态编码与功能分解设计","authors":"S. Pagey, S. Sherlekar, G. Venkatesh","doi":"10.1109/ATS.1993.398820","DOIUrl":null,"url":null,"abstract":"In a previous paper, we presented a functional decomposition technique for low cost self-checking realizations of combinational circuits. This technique can be applied directly to the design of the next state logic of FSMs. In this paper, we present a methodology for good state encoding which results in a low cost self-checking realization of the FSM. The state encoding problem for self-checking realizations of FSMs consists of (a) the choice of a code space for state encoding, and (b) the assignment of codewords to individual states. While (b) can be solved using existing state assignment tools, (a) is addressed for the first time in this paper.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"State encoding and functional decomposition for self-checking sequential circuit design\",\"authors\":\"S. Pagey, S. Sherlekar, G. Venkatesh\",\"doi\":\"10.1109/ATS.1993.398820\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In a previous paper, we presented a functional decomposition technique for low cost self-checking realizations of combinational circuits. This technique can be applied directly to the design of the next state logic of FSMs. In this paper, we present a methodology for good state encoding which results in a low cost self-checking realization of the FSM. The state encoding problem for self-checking realizations of FSMs consists of (a) the choice of a code space for state encoding, and (b) the assignment of codewords to individual states. While (b) can be solved using existing state assignment tools, (a) is addressed for the first time in this paper.<<ETX>>\",\"PeriodicalId\":228291,\"journal\":{\"name\":\"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-11-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1993.398820\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1993.398820","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
State encoding and functional decomposition for self-checking sequential circuit design
In a previous paper, we presented a functional decomposition technique for low cost self-checking realizations of combinational circuits. This technique can be applied directly to the design of the next state logic of FSMs. In this paper, we present a methodology for good state encoding which results in a low cost self-checking realization of the FSM. The state encoding problem for self-checking realizations of FSMs consists of (a) the choice of a code space for state encoding, and (b) the assignment of codewords to individual states. While (b) can be solved using existing state assignment tools, (a) is addressed for the first time in this paper.<>