Achieving minimal hardware multiple signature analysis for BIST

Abstract

This paper proposes a new method for achieving minimal hardware multiple intermediate signature analysis whereby n signatures are checked against a single reference. With a single reference, checking multiple signatures requires the same amount of hardware as for checking only one. However, checking multiple signatures has many advantages. In comparison to the method described by Y. Wie and A Ivahou (1993) in [13], the proposed method is faster by a factor of 2/sup k/, where k is the signature size. E.g., to check two 16-bit signatures against a single reference, the total CPU time cost (Sun Sparcstation 2) is less than 4 sec. for a test length of up to 2/sup 20/, independently of the size of the circuit under test (CUT).<>