P.R. Sureshkumar, J. Jacob, M. Srinivas, V. Agrawal
{"title":"FASSAD: Fault simulation with sensitivities and depth-first propagation","authors":"P.R. Sureshkumar, J. Jacob, M. Srinivas, V. Agrawal","doi":"10.1109/ATS.1993.398781","DOIUrl":null,"url":null,"abstract":"We use depth-first propagation of fault effects to quickly terminate the simulation of detected faults. Using the true logic states of signals, gates are classified as either definitely sensitive or potentially sensitive. Based upon this classification, we formulate rules for efficient propagation of faulty circuit events. These techniques are implemented in a single fault propagation (SFP) program. Results on benchmark circuits demonstrate that the depth-first propagation requires smaller number of gate evaluations compared to the conventional breadth-first propagation. Our technique takes smaller CPU time compared to a concurrent fault simulator for the ISCAS85 benchmarks and a differential parallel fault simulator for some of the ISCAS89 sequential benchmarks.<<ETX>>","PeriodicalId":228291,"journal":{"name":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1993.398781","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
We use depth-first propagation of fault effects to quickly terminate the simulation of detected faults. Using the true logic states of signals, gates are classified as either definitely sensitive or potentially sensitive. Based upon this classification, we formulate rules for efficient propagation of faulty circuit events. These techniques are implemented in a single fault propagation (SFP) program. Results on benchmark circuits demonstrate that the depth-first propagation requires smaller number of gate evaluations compared to the conventional breadth-first propagation. Our technique takes smaller CPU time compared to a concurrent fault simulator for the ISCAS85 benchmarks and a differential parallel fault simulator for some of the ISCAS89 sequential benchmarks.<>