A C-testable DCVS GF(2/sup m/) multiplier

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS) Pub Date : 1993-11-16 DOI:10.1109/ATS.1993.398805

T. Chang, J.H.T. Chen, J. Hsu

引用次数: 0

Abstract

A C-testable design, which requires only five test patterns, for dynamic clocked differential cascode voltage switch (DCVS) GF(2/sup m/) multiplier circuit is proposed. The hardware overhead includes two extra control lines and m XOR gates. For simplicity, the area overhead in transistor counts is /sup 1//sub 3m+1/ for a GF(2/sup m/) multiplier.<>

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可c测试的DCVS GF(2/sup m/)乘法器

针对动态时钟差分级联电压开关(DCVS)的GF(2/sup m/)乘法器电路，提出了一种只需5种测试模式即可进行c测试的设计方案。硬件开销包括两个额外的控制线和m个异或门。为简单起见，晶体管计数的面积开销为/sup 1//sub 3m+1/对于GF(2/sup m/)乘法器

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

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