Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium最新文献

{"title":"Reducing hot spots and junction temperatures of integrated circuits using carbon composite in a printed circuit board and substrate","authors":"K. Vasoya","doi":"10.1109/STHERM.2006.1625235","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625235","url":null,"abstract":"Carbon composite laminate is used in the integral structure of printed circuit boards (PCB) today to spread the heat from the heat source mounted on the surface. The thermal conductivity of carbon fiber used in the composite is lateral and ranging from 10W/m.K to 600W/m.K. This lateral property results in high thermal conductivity in-plane, opposed to the through-plane of composite. This anisotropic thermal property has the unique advantage of spreading heat throughout the entire surface area of the printed circuit board. The composite layer can be used as an internal thermal plane layer and heat from the heat source can be conducted to the carbon composite layer through thermal vias. The composite layer can also be used as a ground or power layer to improve heat conduction from the heat source to the carbon composite layer through all ground or power via connections. Carbon composite also acts as an internal heat spreader thus, concentrated heat from the high power ICs can be spread out to entire plane area. This reduces or eliminates localized \"hot spots\" and reduces junction temperature of the IC components. Further heat can be removed from the PCB surface using a forced or natural convection cooling mechanism. This type of internal heat spreading method can be extremely advantageous in an application such as a memory module which uses stacked devices. In a stacked memory module, the inside DRAM is trapped between outside DRAM and the PCB. The outside DRAM receives fanned air but the inside DRAM has no way to dissipate heat to the environment. A series of tests have been performed and have shown 8-12degC temperature differences from standard materials using carbon composite in the PCB. Beside the thermal benefits, carbon composite has several other benefits. It allows the designer to tailor the coefficient of thermal expansion (CTE) of the PCB to match with the CTE of components, it increases rigidity/stiffness by magnitudes, and it does not add any weight over FR4, polyimide and standard materials. A designer can reduce hot spots and the junction temperature of the hot components by selecting the proper carbon composite type and selecting the proper number of composite layers in the structure of the PCB. Several other materials can also be used as a thermal plane such as copper, copper-moly-copper (CMC), copper-Invar-copper (CIC), aluminum nitride and aluminum silicon carbide (AlSiC)","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121665607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fundamentals of a floating loop concept based on R134a refrigerant cooling of high heat flux electronics","authors":"C. Ayers, J. S. Hsu, K. Lowe","doi":"10.1109/STHERM.2006.1625207","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625207","url":null,"abstract":"The Oak Ridge National Laboratory (ORNL) Power Electronics and Electric Machinery Research Center (PEEMRC) has been developing technologies to address the thermal concerns associated with hybrid electric vehicles (HEVs). This work is part of the ongoing FreedomCAR and Vehicle Technologies program (FCVT), performed for the Department of Energy (DOE). Removal of the heat generated from electrical losses in traction motors and their associated power electronics is essential for the reliable operation of motors and power electronics. As part of a larger thermal management project, which includes shrinking inverter size and direct cooling of electronics, ORNL has developed U.S. Patent No. 6,772,603 B2, Methods and Apparatus for Thermal Management of Vehicle Systems and Components (Hsu, 2004), and patent pending floating loop system for cooling integrated motors and inverters using hot liquid refrigerant (Hsu, 2004). The floating-loop system provides a large coefficient of performance (COP) for hybrid-electric drive component cooling. This loop (based on R-134a) shares a vehicle's existing air-conditioning (AC) condenser, which dissipates waste heat to the ambient air. Because the temperature requirements for cooling of power electronics and electric machines are not as low as that required for passenger compartment air, this adjoining loop can operate on the high-pressure side of the existing AC system. This arrangement also allows for the floating loop to run without the need for the compressor and only needs a small pump to move the liquid refrigerant. For the design to be viable, the loop must not adversely affect the existing system. The loop would also provide a high COP, a flat temperature profile, and a low pressure drop. The floating-loop test prototype has been successfully integrated into a 9 kW automobile passenger AC system. In this configuration, the floating loop has been tested up to 2 kW of heat rejected during operation with and without the automotive AC system running. The floating-loop system has demonstrated a very respectable COP of 40-45, as compared to a typical AC system COP of about 2-4. The estimated required waste-heat load for future HEV cooling applications is 5.5 kW, and the existing system should be easily scalable to this larger load","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128212466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The impact of thermal imaging procedures on bare die leading toward chip layout design or wafer processing modifications","authors":"K. Rispoli, L. Gould, J. Mandry, P. Delivorias","doi":"10.1109/STHERM.2006.1625216","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625216","url":null,"abstract":"Instituting dimensional reductions in the layout of CMOS semiconductor chips can lead to unwanted conduction paths significant enough to impact the performance and reliability of the subsequent fabricated integrated circuit. Positive location and identification of the suspect areas is required for the determination of root cause and to enable corrective action to eliminate or minimize the unwanted conduction paths. Empirical methods have to be employed to identify suspect areas since EDA vendors do not have CAD tools sufficiently capable of identifying the suspect areas during the design phase of a complicated high performance integrated circuit. Applying varied thermal imaging procedures and analytical techniques on specially assembled bare chips with defined limited performance identified problematic chip substrate regions and subsequent current conduction through the substrate as the problem in those regions. Corrective chip design layout and assembly techniques were instituted to achieve the required isolation. Although corrective action was achieved through chip design layout modifications, an outline of the wafer processing technology employed will be presented to designate the questionable areas with possible fabrication alterations to avoid the conduction paths encountered","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130655441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dbc (direct bond copper) substrate with integrated flat heat pipe","authors":"J. Schulz-Harder, J.B. Dezord, C. Schaeffer, Y. Avenas, O. Puig, A. Rogg, K. Exel, A. Utz-Kistner","doi":"10.1109/STHERM.2006.1625221","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625221","url":null,"abstract":"A novel heat pipe design was developed consisting or a ceramic substrate sandwich with integrated flat heat pipe. On both sides of the heat pipe active electronic components, such as IGBT's or MOSFET's, can be mounted on an etched copper circuit. Heat densities over 80 W/cm2 can be dissipated easily. The functionality is independent of the working position either horizontal or vertical. The heat pipe can be used to an internal pressure over 7 bars without cracking the ceramic substrate. All requirements for space applications could be fulfilled. First application is foreseen for cooling DC-DC converters in satellites","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131389136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Methodology of optimization for microchannel heat exchanger","authors":"Heesung Park, Jongln Jo, Jae-Young Chang, Sunsoo Kim","doi":"10.1109/STHERM.2006.1625208","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625208","url":null,"abstract":"Heat generation from very large-scale integrated (VLSI) circuits increases with the advent of high-density integrated circuit technology. One of the promising techniques is liquid cooling by using microchannel heat exchanger. This work proposes a scheme for microchannel heat exchanger optimization with the constraint of pump. The cooling performance of microchannel heat exchanger was analyzed by constraining the flow rate and pressure drop of the pump used in this work. The minimum thermal resistance of the microchannel heat exchanger was calculated by using channel flow theory. And experiments were also conducted to verify the results from the channel flow theory. Based on the optimization process from this paper, the dimension of microchannel heat exchanger is proposed for maximum cooling efficiency with the given pump","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115075998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design rule for minimizing thermal resistance in a non~uniformly powered microprocessor","authors":"A. Kaisare, D. Agonafer, A. Haji-shiekh, G. Chrysler, R. Mahajan","doi":"10.1109/STHERM.2006.1625214","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625214","url":null,"abstract":"Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed and the instruction execution time has increased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. Previous work (Kaisare, 2005) has been done to minimize the thermal resistance of the package by optimizing the distribution of the nonuniform powered functional blocks with a specific power matrix. The objective of this paper is to come up with a design rule in general for functional block distribution in a nonuniformly powered microarchitecture. In order to model the nonuniform power dissipation on the silicon chip, the chip surface area is divided into different cases such as 3 times 3, 4 times 4 etc. of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements A design rule for minimizing thermal resistance will be developed for any number of functional blocks for a given nonuniformly powered microprocessor. The commercial finite element code ANSYSreg is used for this analysis","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115745929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microchip cooling module based on FC72 slot jet arrays without cross-flow","authors":"M. Fabbri, A. Wetter, B. Mayer, T. Brunschwiler, B. Michel, H. Rothuizen, R. Linderman, U. Kloter","doi":"10.1109/STHERM.2006.1625206","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625206","url":null,"abstract":"In view of the rapid increase of microchip power densities, thermal management has become considerably more challenging. This work presents the first results of an effort aimed at developing a liquid-based cooling module capable of handling high heat fluxes. Four modules 20 times 20 times 2 mm3 in size, containing as many as 120 planar (\"slot\") jets and a drainage channel system that prevented any cross-flow effect, were tested using FC72 as test fluid. The jet hydraulic diameters were between 173 and 310 mum, with larger drainage channels, 701 to 955 mum in diameter, located between the inlet jets. A custom-made heater resembling an actual microchip was manufactured from silicon and equipped with temperature sensors. The effects of the flow rate, the inlet liquid temperature, the gap between impinged surface and nozzle plate, and different module geometries are discussed. A maximum of 92 W/cm2 was removed at a junction temperature of 85 degC using a coolant flow of 1.46 l/min and an inlet temperature of 20 degC","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125855085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of thin film microcoolers for hot spot removal in packaged integrated circuit chips","authors":"K. Fukutani, A. Shakouri","doi":"10.1109/STHERM.2006.1625218","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625218","url":null,"abstract":"Hot spot removal using monolithic thin film microcoolers in a packaged chip is analyzed via an effective one-dimensional electrothermal model taking into account the three-dimensional heat and current flow in the substrate region. Various ideal and nonideal parameters that affect the maximum cooling performance for the thin film microcoolers are discussed. Our results show that there is an optimum thin film thickness and current that give the highest cooling density at the hot spot and further thinning of thin film thickness degrades cooling performance due to finite thermal resistance between the hot side of the Si substrate and ambient, and due to electrical contact resistance. An optimally designed Si/SiGe superlattice thin film microcooler with material thermoelectric figure-of-merit, ZT, of ~0.12 is able to lower the local hot spot temperature compared to that calculated from the Si substrate with no Peltier effects. At Qh = 300 W/cm the temperature difference between the passive bulk Si substrate and thin film microcooler configuration reaches more than 7.0 degC for a hot spot 50 microns in diameter. Finally, the effect of material properties, chip to ambient thermal resistance and contact resistance on the cooling performance is also discussed. If the material ZT is improved by a factor of 5, hot spot temperature can be lowered by 10-30 C at a heat flux of 1000 W/cm2. Seebeck coefficient improvement will have a higher impact on maximum cooling than the reduction in material's thermal conductivity or its electrical resistivity","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134011393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal packaging - the moving frontier","authors":"A. Bar-Cohen","doi":"10.1109/STHERM.2006.1625197","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625197","url":null,"abstract":"Summary form only given. Revolutionary and evolutionary advances in thermal packaging technology, computational techniques, and diagnostics during the past 50 years have underpinned the continuous improvement in the performance, packaging density, and reliability achieved in solid state electronic products. Rising chip heat fluxes and packaging density, driven by Moore's Law, have necessitated ever more aggressive cooling techniques, capable of reducing the junction-to-ambient thermal resistance while meeting the cost, volume, and weight constraints appropriate to each class of electronic equipment. As these needs have escalated, attention has shifted from the external packaging levels towards the module and board level, then the package level, and is today focused on heat removal at the chip level. Current trends suggest that on-chip hot spots and 3-dimensional microsystems will drive the choice of future thermal packaging technology; that thermal modeling tools will need to be more fully integrated with chip-level ECAD and power management algorithms, and that spatially and temporally variable cooling rates will be used to extend and optimize the performance of nanoelectronic devices. Periodic thermal packaging paradigm shifts, along with rapid intra-generational evolutionary improvements, have facilitated the effective utilization of successive generations of solid state device technology and must continue to do so, if the full promise of emerging nanoelectronic technology is to be realized","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126654172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-domain simulation and measurement of power LED-s and power LED assemblies","authors":"A. Poppe, G. Farkas, V. Székely, G. Horváth, M. Rencz","doi":"10.1109/STHERM.2006.1625227","DOIUrl":"https://doi.org/10.1109/STHERM.2006.1625227","url":null,"abstract":"Besides their electrical properties the optical parameters of LEDs also depend on junction temperature. For this reason thermal characterization and thermal management plays important role in case of power LEDs, necessitating tools both for physical measurements and simulation. The focus of this paper is a combined electrical, thermal and optical characterization of such devices. In terms of simulation a novel approach of board-level electro-thermal simulation is presented whereas in terms of measurement, a combined thermal and radiometric characterization method is discussed","PeriodicalId":222515,"journal":{"name":"Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131462489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}