Design rule for minimizing thermal resistance in a non~uniformly powered microprocessor

Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium Pub Date : 2006-03-14 DOI:10.1109/STHERM.2006.1625214

A. Kaisare, D. Agonafer, A. Haji-shiekh, G. Chrysler, R. Mahajan

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引用次数: 6

Abstract

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed and the instruction execution time has increased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. Previous work (Kaisare, 2005) has been done to minimize the thermal resistance of the package by optimizing the distribution of the nonuniform powered functional blocks with a specific power matrix. The objective of this paper is to come up with a design rule in general for functional block distribution in a nonuniformly powered microarchitecture. In order to model the nonuniform power dissipation on the silicon chip, the chip surface area is divided into different cases such as 3 times 3, 4 times 4 etc. of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements A design rule for minimizing thermal resistance will be developed for any number of functional blocks for a given nonuniformly powered microprocessor. The commercial finite element code ANSYSreg is used for this analysis

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非均匀供电微处理器中热阻最小的设计规则

微处理器在功能、复杂性和性能方面不断发展。当前一代的微处理器将逻辑和二级(L2)缓存存储器等功能组件集成到微处理器架构中。随着时钟速度和指令执行时间的提高，微处理器的功能集成化使微处理器的性能得到了提高。然而，集成给微处理器的热设计和管理带来了一层复杂性。作为功能集成的直接结果，微处理器上的功率图是高度不均匀的，并且芯片表面均匀热流的假设是无效的。以前的工作(Kaisare, 2005)已经完成了通过优化具有特定功率矩阵的非均匀供电功能块的分布来最小化封装的热阻。本文的目的是为非均匀动力微体系结构中的功能块分布提出一个通用的设计规则。为了模拟硅芯片上的非均匀功耗，将芯片表面积划分为功率矩阵的3 × 3、4 × 4等不同情况，并用一个矩阵空间表示具有恒定热流的不同功能块。最后，利用有限元程序对功能块的相对位置进行了优化，以使结温Tj最小。因此可以找到最佳的减少Tjmax的方法。在现实中(以及以后)，必须对任意2个(或更多)功能块的最大分离加以限制，以满足电气时序和计算性能要求。对于给定的非均匀供电微处理器的任意数量的功能块，将制定最小化热阻的设计规则。使用商业有限元代码ANSYSreg进行分析

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Twenty-Second Annual IEEE Semiconductor Thermal Measurement And Management Symposium

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