Optimization of thin film microcoolers for hot spot removal in packaged integrated circuit chips

Abstract

Hot spot removal using monolithic thin film microcoolers in a packaged chip is analyzed via an effective one-dimensional electrothermal model taking into account the three-dimensional heat and current flow in the substrate region. Various ideal and nonideal parameters that affect the maximum cooling performance for the thin film microcoolers are discussed. Our results show that there is an optimum thin film thickness and current that give the highest cooling density at the hot spot and further thinning of thin film thickness degrades cooling performance due to finite thermal resistance between the hot side of the Si substrate and ambient, and due to electrical contact resistance. An optimally designed Si/SiGe superlattice thin film microcooler with material thermoelectric figure-of-merit, ZT, of ~0.12 is able to lower the local hot spot temperature compared to that calculated from the Si substrate with no Peltier effects. At Qh = 300 W/cm the temperature difference between the passive bulk Si substrate and thin film microcooler configuration reaches more than 7.0 degC for a hot spot 50 microns in diameter. Finally, the effect of material properties, chip to ambient thermal resistance and contact resistance on the cooling performance is also discussed. If the material ZT is improved by a factor of 5, hot spot temperature can be lowered by 10-30 C at a heat flux of 1000 W/cm2. Seebeck coefficient improvement will have a higher impact on maximum cooling than the reduction in material's thermal conductivity or its electrical resistivity