Thermal packaging - the moving frontier

Summary form only given. Revolutionary and evolutionary advances in thermal packaging technology, computational techniques, and diagnostics during the past 50 years have underpinned the continuous improvement in the performance, packaging density, and reliability achieved in solid state electronic products. Rising chip heat fluxes and packaging density, driven by Moore's Law, have necessitated ever more aggressive cooling techniques, capable of reducing the junction-to-ambient thermal resistance while meeting the cost, volume, and weight constraints appropriate to each class of electronic equipment. As these needs have escalated, attention has shifted from the external packaging levels towards the module and board level, then the package level, and is today focused on heat removal at the chip level. Current trends suggest that on-chip hot spots and 3-dimensional microsystems will drive the choice of future thermal packaging technology; that thermal modeling tools will need to be more fully integrated with chip-level ECAD and power management algorithms, and that spatially and temporally variable cooling rates will be used to extend and optimize the performance of nanoelectronic devices. Periodic thermal packaging paradigm shifts, along with rapid intra-generational evolutionary improvements, have facilitated the effective utilization of successive generations of solid state device technology and must continue to do so, if the full promise of emerging nanoelectronic technology is to be realized