18th International Symposium on VLSI Design and Test最新文献_第2页

Design of a fault tolerant low-order interleaved memory based on the concept of bubble-stack an image storage perspective 基于气泡堆栈的低阶交错容错存储器设计

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881087

Somak R. Das, Sowvik Dey

引用次数: 2

A thermal aware 3D IC partitioning technique 一种热感知的3D IC分区技术

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881069

Sabyasachee Banerjee, S. Majumder

{"title":"A thermal aware 3D IC partitioning technique","authors":"Sabyasachee Banerjee, S. Majumder","doi":"10.1109/ISVDAT.2014.6881069","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881069","url":null,"abstract":"On-chip power density plays a major role in case of Highperformance VLSI circuits. 3D chips have significantly larger power densities compared to their 2D counterparts due to increased scaling of technology and also increased number of components with higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Thermal problems and limitations on inter-layer via (TSV) densities are important design constraints on three-dimensional integrated circuits (3D ICs). In this paper we introduce an algorithm where the modules with relatively high power densities are placed at the bottom layer and subsequently modules with relatively less power densities are placed on more higher layers. The temperatures of the layers vary in a non-increasing manner from the bottommost layer to the topmost layer to ensure efficient heat dissipation of the whole chip, which means we may require lesser number of heat TSVs to dissipate heat. Along with this thermal aware partitioning technique, we also tried to minimize the number of inter-layer vias (Signal TSVs) by swapping some modules across layers, in exchange of little increment in the area of the layer that has the maximum area in the circuitry. The experimental results we got are quite encouraging.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121116810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Layout-aware signal selection in reconfigurable architectures 可重构结构中感知布局的信号选择

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881078

Prateek Thakyal, P. Mishra

引用次数: 2

250mA ultra low drop out regulator with high slew rate double recycling folded cascode error amplifier 250mA超低差调节器，高摆压率双循环折叠级联误差放大器

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881067

S. Patri, S. Alapati, S. Chowdary, K. Prasad

引用次数: 7

All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit 基于可逆顺序电路的Mach-Zehnder干涉仪全光学实现

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881079

P. Dutta, Chandan Bandyopadhyay, H. Rahaman

引用次数: 3

Design of tunnel FET based low power digital circuits 基于隧道场效应管的低功耗数字电路设计

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881075

A. Kamal, Bindu Boby

引用次数: 4

Tunnel FET based low voltage static vs dynamic logic families for energy efficiency 基于隧道场效应管的低电压静态与动态逻辑系列的能源效率

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881042

K. Subramanyam, Sadulla Shaik, R. Vaddi

引用次数: 10

A 32×32 CMOS image sensor: Tested using process and temperature compensated voltage controlled current source 一种32×32 CMOS图像传感器:使用工艺和温度补偿电压控制电流源进行测试

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881073

P. Kumar, M. Seenivasan

引用次数: 0

Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model 基于窗口峰值功率模型的粒子群算法指导多频功耗感知的片上系统测试调度

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881089

R. Karmakar, Aditya Agarwal, S. Chattopadhyay

引用次数: 2

Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors 高q变宽变间距、平面和三维堆叠螺旋电感的设计与建模

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881053

R. Manikandan, V. Vanukuru, A. Chakravorty, B. Amrutur

{"title":"Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors","authors":"R. Manikandan, V. Vanukuru, A. Chakravorty, B. Amrutur","doi":"10.1109/ISVDAT.2014.6881053","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881053","url":null,"abstract":"Layout optimized planar spiral inductors using variable width (W) and spacing (S) across their turns are known to exhibit higher quality factors (Q). In this paper, we explore the performance improvement of 3-dimensional, series-stacked, parallel-stacked, single ended, and symmetric inductor configurations with variable W&S across their turns. Parameterized cells for the aforementioned complex variable W&S inductor structures are developed in cadence using SKILL scripts for automatic generation of optimized inductor layouts with improved quality factors. The analyzed standard (constant W&S) and layout optimized (variable W&S) inductors are fabricated in a 0.18 μm silicon on insulator process. Measurement results show more than 20% improvement in quality factor for the 3-D stacked variable W&S inductor topologies. Furthermore, an accurate, scalable, and broadband compact inductor model was developed and is shown to capture the improved Q characteristics across the analyzed inductor topologies. A complementary LC-tank voltage controlled oscillator with layout optimized inductors, operating over 2.4-2.5 GHz frequency range was simulated using these developed compact models and is shown to exhibit an improved phase noise characteristics with better figure of merit.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122506167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10