{"title":"Layout-aware signal selection in reconfigurable architectures","authors":"Prateek Thakyal, P. Mishra","doi":"10.1109/ISVDAT.2014.6881078","DOIUrl":null,"url":null,"abstract":"Post-silicon validation is an important and increasingly complex task in SoC design methodology. One of the major challenges in post-silicon debug is the limited observability of internal signals. Existing signal selection techniques try to maximize observability by selecting a small set of profitable trace signals. Unfortunately, these techniques do not consider design constraints such as routing congestion in reconfigurable architectures. In this paper, we propose a layout-aware signal selection algorithm that takes into account both observability and routing congestion in field-programmable gate array (FPGA). Our experimental results demonstrate that our approach can tradeoff between observability and wire-length reduction in FPGA-based designs.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"333 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"18th International Symposium on VLSI Design and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVDAT.2014.6881078","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Post-silicon validation is an important and increasingly complex task in SoC design methodology. One of the major challenges in post-silicon debug is the limited observability of internal signals. Existing signal selection techniques try to maximize observability by selecting a small set of profitable trace signals. Unfortunately, these techniques do not consider design constraints such as routing congestion in reconfigurable architectures. In this paper, we propose a layout-aware signal selection algorithm that takes into account both observability and routing congestion in field-programmable gate array (FPGA). Our experimental results demonstrate that our approach can tradeoff between observability and wire-length reduction in FPGA-based designs.