Layout-aware signal selection in reconfigurable architectures

Prateek Thakyal, P. Mishra
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引用次数: 2

Abstract

Post-silicon validation is an important and increasingly complex task in SoC design methodology. One of the major challenges in post-silicon debug is the limited observability of internal signals. Existing signal selection techniques try to maximize observability by selecting a small set of profitable trace signals. Unfortunately, these techniques do not consider design constraints such as routing congestion in reconfigurable architectures. In this paper, we propose a layout-aware signal selection algorithm that takes into account both observability and routing congestion in field-programmable gate array (FPGA). Our experimental results demonstrate that our approach can tradeoff between observability and wire-length reduction in FPGA-based designs.
可重构结构中感知布局的信号选择
晶片后验证是SoC设计方法中一项重要且日益复杂的任务。后硅调试的主要挑战之一是内部信号的有限可观测性。现有的信号选择技术试图通过选择一小组有利可图的跟踪信号来最大化可观测性。不幸的是,这些技术没有考虑设计约束,比如可重构架构中的路由拥塞。在本文中,我们提出了一种考虑现场可编程门阵列(FPGA)中可观察性和路由拥塞的布局感知信号选择算法。我们的实验结果表明,我们的方法可以在基于fpga的设计中的可观察性和线长减少之间进行权衡。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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