A thermal aware 3D IC partitioning technique

Sabyasachee Banerjee, S. Majumder
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引用次数: 2

Abstract

On-chip power density plays a major role in case of Highperformance VLSI circuits. 3D chips have significantly larger power densities compared to their 2D counterparts due to increased scaling of technology and also increased number of components with higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Thermal problems and limitations on inter-layer via (TSV) densities are important design constraints on three-dimensional integrated circuits (3D ICs). In this paper we introduce an algorithm where the modules with relatively high power densities are placed at the bottom layer and subsequently modules with relatively less power densities are placed on more higher layers. The temperatures of the layers vary in a non-increasing manner from the bottommost layer to the topmost layer to ensure efficient heat dissipation of the whole chip, which means we may require lesser number of heat TSVs to dissipate heat. Along with this thermal aware partitioning technique, we also tried to minimize the number of inter-layer vias (Signal TSVs) by swapping some modules across layers, in exchange of little increment in the area of the layer that has the maximum area in the circuitry. The experimental results we got are quite encouraging.
一种热感知的3D IC分区技术
片上功率密度在高性能VLSI电路中起着重要的作用。与2D芯片相比,3D芯片具有更大的功率密度,这是由于技术规模的增加,以及频率和带宽更高的组件数量的增加。消耗的功率通常转化为散失的热量,影响芯片的性能和可靠性。热问题和层间通孔(TSV)密度限制是三维集成电路(3D ic)设计的重要制约因素。在本文中,我们介绍了一种算法,该算法将功率密度相对较高的模块放置在底层,随后将功率密度相对较低的模块放置在更高的层。为了保证整个芯片的高效散热,从最底层到最顶层各层的温度变化不增加,这意味着我们可能需要更少的热tsv来散热。除了这种热感知分区技术,我们还试图通过跨层交换一些模块来最小化层间通孔(信号tsv)的数量,以换取电路中面积最大的层面积的微小增加。我们得到的实验结果相当令人鼓舞。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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