A thermal aware 3D IC partitioning technique

Abstract

On-chip power density plays a major role in case of Highperformance VLSI circuits. 3D chips have significantly larger power densities compared to their 2D counterparts due to increased scaling of technology and also increased number of components with higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Thermal problems and limitations on inter-layer via (TSV) densities are important design constraints on three-dimensional integrated circuits (3D ICs). In this paper we introduce an algorithm where the modules with relatively high power densities are placed at the bottom layer and subsequently modules with relatively less power densities are placed on more higher layers. The temperatures of the layers vary in a non-increasing manner from the bottommost layer to the topmost layer to ensure efficient heat dissipation of the whole chip, which means we may require lesser number of heat TSVs to dissipate heat. Along with this thermal aware partitioning technique, we also tried to minimize the number of inter-layer vias (Signal TSVs) by swapping some modules across layers, in exchange of little increment in the area of the layer that has the maximum area in the circuitry. The experimental results we got are quite encouraging.