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An FPGA implementation of image signature based visual-saliency detection 基于图像签名的视觉显著性检测的FPGA实现
18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881060
Bhavit Kaushik, Ravi Saini, Anil K. Saini, Sanjay Singh, A. S. Mandal
{"title":"An FPGA implementation of image signature based visual-saliency detection","authors":"Bhavit Kaushik, Ravi Saini, Anil K. Saini, Sanjay Singh, A. S. Mandal","doi":"10.1109/ISVDAT.2014.6881060","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881060","url":null,"abstract":"In this paper we present a prototype FPGA design for Saliency detection based on image signature technique to support embedded vision application. Visual attention supports biological vision to restrict our gaze only to the region of interest of a visual scene. We propose a pipelined architecture using Gaussian filter, Discrete Cosine Transform, Inverse Discrete Cosine Transform and Averaging block that is shared across the system. The investigation involves simulation and synthesis of VHDL code using ModelSimTM and Xilinx Synthesis Toolbox as design environments. Due to real-time requirements and computational-cost constraints in embedded systems, it is necessary to accelerate Saliency detection algorithm by hardware implementation. Experiment shows that the proposed hardware has the maximum clock speed of 160 MHz with Xilinx ML510 (Virtex-5 FX130T) FPGA platform.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121145965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Signature analysis for synthesis of reversible circuit 可逆电路合成的特征分析
18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881043
P. Das, Bikromadittya Mondal
{"title":"Signature analysis for synthesis of reversible circuit","authors":"P. Das, Bikromadittya Mondal","doi":"10.1109/ISVDAT.2014.6881043","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881043","url":null,"abstract":"The paper proposes a novel synthesis of reversible circuit through signature analysis. A set of grouping rules are proposed that are used for minimizing the output expressions and thus reducing the number of reversible gates to construct the circuit. Experimental results depict a huge amount of reduction on CNOT gate count and quantum cost.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116263778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A BDD based secure hardware design method to guard against power analysis attacks 一种基于BDD的安全硬件设计方法，以防范功率分析攻击
18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881088
P. De, K. Banerjee, C. Mandal
{"title":"A BDD based secure hardware design method to guard against power analysis attacks","authors":"P. De, K. Banerjee, C. Mandal","doi":"10.1109/ISVDAT.2014.6881088","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881088","url":null,"abstract":"Power analysis attacks (PAAs) present a major threat towards safeguarding the secrets of cryptographic systems. We have devised a hardware countermeasure in the form of a Binary Decision Diagram (BDD) based dual-rail circuits and a supporting synthesis procedure. We have, for the first time, used the BDD to model the pre-charge generation logic while designing such a cell. Experimental results demonstrate the resistance against power analysis attacks of circuits developed using this approach, while outperforming other contemporary designs in terms of peak power variance, average power and average current. All results have been obtained using 65nm technology.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123521402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application 超低功耗应用中采用单时钟节能绝热逻辑的顺序电路设计
18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881076
M. Chanda, A. S. Chakraborty, S. Nag, Raina Modak
{"title":"Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application","authors":"M. Chanda, A. S. Chakraborty, S. Nag, Raina Modak","doi":"10.1109/ISVDAT.2014.6881076","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881076","url":null,"abstract":"This paper presents energy efficient pre-settable adiabatic sequential circuits based on the Energy efficient adiabatic Logic (EEAL). Adiabatic Flip-flops and sequential circuits have been implemented using EEAL style in a TSMC 0.18 μm CMOS technology. Extensive CADENCE simulations show that EEAL based sequential circuit consumes only 22%-35% of total energy consumed by others imperative logic styles.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"322 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132426368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications 基于无结FinFET的电路/SRAM应用中的高介电常数间隔效应
18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881054
Dilsukh Nehra, P. Pal, B. Kaushik, S. Dasgupta
{"title":"High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications","authors":"Dilsukh Nehra, P. Pal, B. Kaushik, S. Dasgupta","doi":"10.1109/ISVDAT.2014.6881054","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881054","url":null,"abstract":"In this paper, we present the impact of spacer dielectric on a junctionless transistor (JLT) FinFET based circuit/SRAM memory cell. JLT FinFETs with high-k spacers provide excellent electrostatic integrity as well as reduction in short channel effects (SCEs). Fringing electric field through spacer increases effective channel length in the OFF-state, whereas in ON-state it is unaffected. It is observed that the drive current, leakage current, drain induced barrier lowering (DIBL) and sub-threshold swing (SS) are improved. The JLT structure with spacers leads to better noise-margins of CMOS inverter. Moreover, the JLT architecture also improves the performance of SRAM in terms of static-noise margins (SNMs) and leakage power with increase in high-k spacer value. High-k spacer increase the capacitance of the device, so ring oscillator delay and SRAM access times are degraded.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127291768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An analytical delay model for CMOS Inverter-Transmission Gate structure CMOS逆变-传输门结构的解析延迟模型
18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881038
Mohammad Shueb Romi, N. Alam, M. Y. Yasin
{"title":"An analytical delay model for CMOS Inverter-Transmission Gate structure","authors":"Mohammad Shueb Romi, N. Alam, M. Y. Yasin","doi":"10.1109/ISVDAT.2014.6881038","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881038","url":null,"abstract":"This paper presents a novel approach for delay modeling of Inverter followed by Transmission Gate (Inv-TG) structure. Our model is novel in the sense that it considers the series stack effect along with the internal node voltage and parasitic capacitance while treating the Inv-TG structure as a single entity. Subsequently, we propose a methodology to incorporate the effect of Process-Voltage-Temperature (PVT) variations in the derived model. We compare our derived model against the SPICE simulation results using 32nm Predictive Technology Model. We observe that the error in the estimated delay using our model is within the acceptable range (<;10%).","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128547680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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