18th International Symposium on VLSI Design and Test最新文献_第5页

A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications 45 uW 13 pJ/反步7.4-ENOB 40 kS/s SAR ADC，用于数字微流控生物芯片应用

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881068

Indrajit Das, Manodipan Sahoo, P. Roy, H. Rahaman

引用次数: 3

Distributed adaptive routing for spidergon NoC 蜘蛛蛛NoC的分布式自适应路由

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881058

Rimpy Bishnoi, P. K. Srivastava, V. Laxmi, M. Gaur, Apoorva Sikka

引用次数: 10

Deterministic seed selection and pattern reduction in Logic BIST 逻辑BIST的确定性种子选择与模式约简

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881039

R. Bhakthavatchalu, Sreeja Krishnan, V. Vineeth, M. Nirmala Devi

引用次数: 18

An approach for efficient FIR filter design for hearing aid application 一种用于助听器的高效FIR滤波器设计方法

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881051

Srinivasa Reddy Kotha, Devendra Bilaye, Utkarsh Jain, S. K. Sahoo

引用次数: 5

Artificial neural network modelling of ADS designed Double Pole Double Throw switch ADS双极双投开关的人工神经网络建模

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881066

S. Majumdar, Mohd. Zuhair, D. Biswas

引用次数: 4

An FPGA implementation of image signature based visual-saliency detection 基于图像签名的视觉显著性检测的FPGA实现

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881060

Bhavit Kaushik, Ravi Saini, Anil K. Saini, Sanjay Singh, A. S. Mandal

引用次数: 2

Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications 低功耗SoC中22nm节点外延δ掺杂沟道MOS晶体管的反向衬底偏置效应研究

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881050

Debayan Bairagi, Soumya Pandit

{"title":"Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications","authors":"Debayan Bairagi, Soumya Pandit","doi":"10.1109/ISVDAT.2014.6881050","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881050","url":null,"abstract":"This paper presents a comprehensive study of the reverse substrate bias effects of an n-channel epitaxial delta doped channel (EδDC) MOS transistor. The transistor consists of a two layered channel structure, a low doped epitaxial layer followed by a high doped screening layer. The study has been performed using Silvaco TCAD device simulator, calibrated with experimental results. Significant amount of substrate bias effect has been achieved in EδDC transistor in comparison to conventional uniform doped channel transistor (UDC), even for gate length as small as 22nm. The screening phenomenon of the depletion region leads to better control of the channel by substrate and is the key to enhanced substrate bias effect in EδDC transistor. The variations of leakage power dissipation and intrinsic delay with substrate bias have been compared for EδDC and UDC transistor. Significant amount of leakage power saving is achieved in EδDC transistor in comparison to UDC transistor, at the cost of reduced intrinsic speed. The dependence of the substrate sensitivity of the EδDC transistor on the epitxial region thickness and concentration of the high doped screening region has been investigated.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129305709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimization 基于变厚度阶跃式MEMS悬臂设计的生物传感与拉入电压优化建模与仿真

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881055

D. K. Parsediya, Jawar Singh, P. K. Kankar

引用次数: 4

UVM based STBUS verification IP for verifying SoC architectures 基于UVM的STBUS验证IP，用于验证SoC架构

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881037

P. Samanta, Deepak Chauhan, Sujay Deb, P. Gupta

引用次数: 8

An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS 超低功耗MICS/ISM波段发射器，0.18 μm CMOS

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881077

Amitava Ghosh, A. Dhar, Achintya Halder

{"title":"An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS","authors":"Amitava Ghosh, A. Dhar, Achintya Halder","doi":"10.1109/ISVDAT.2014.6881077","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881077","url":null,"abstract":"In this paper the design of an ultra low power transmitter in MICS/ISM band has been presented. The transmitter uses Frequency Shift Keying (FSK) as the modulation scheme. At the heart of the transmitter is an oscillator whose frequency is periodically calibrated. A ring type oscillator has been considered instead of LC type as it reduces the buffer power consumption immediately following the oscillator. Within the ring-based topology a one-stage ring oscillator (basically an astable multivibrator) with fine frequency resolution has been considered for even lower power consumption. The periodically activated frequency calibration system is based on measuring the fraction when the oscillator frequency is divided by a reference frequency and thereby correcting the oscillator frequency. The power amplifier (PA) used is Class-E type. A switch is present to disconnect the frequency calibration unit and turn on the PA after the channel frequencies have been calibrated. The transmitter can work from a data rate of 250kbps to 1Mbps consuming only the minimum bandwidth required for FSK transmission and allowing for simultaneous transmission in the band. It draws an average current of 180 μA from a 1.6V supply achieving the lowest current consumption for a transmitter designed at the specified band and allowing for multichannel operation.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128155189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3