UVM based STBUS verification IP for verifying SoC architectures

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI:10.1109/ISVDAT.2014.6881037

P. Samanta, Deepak Chauhan, Sujay Deb, P. Gupta

引用次数: 8

Abstract

In this paper, we propose the design and development of verification IP (VIP) of STBUS, a widely used bus protocol from STMicroelectronics [1]. VIP is a standalone, pre-verified and built-in verification infrastructure, which can be easily plugged in the simulation-based tests. We have followed Universal Verification Methodology (UVM) for the modelling of the STBUS VIP. Firstly we have verified the important properties of the STBUS protocol and made the VIP. Then we have shown how to use the VIP in a SoC to verify IPs.

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基于UVM的STBUS验证IP，用于验证SoC架构

STBUS是意法半导体(STMicroelectronics)广泛使用的总线协议[1]，本文提出了STBUS验证IP (VIP)的设计与开发。VIP是一个独立的、预先验证的内置验证基础设施，可以很容易地插入到基于模拟的测试中。我们遵循通用验证方法(UVM)对STBUS VIP进行建模。首先，我们验证了STBUS协议的重要特性，并制作了VIP。然后我们展示了如何在SoC中使用VIP来验证ip。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

18th International Symposium on VLSI Design and Test

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