Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications

Abstract

This paper presents a comprehensive study of the reverse substrate bias effects of an n-channel epitaxial delta doped channel (EδDC) MOS transistor. The transistor consists of a two layered channel structure, a low doped epitaxial layer followed by a high doped screening layer. The study has been performed using Silvaco TCAD device simulator, calibrated with experimental results. Significant amount of substrate bias effect has been achieved in EδDC transistor in comparison to conventional uniform doped channel transistor (UDC), even for gate length as small as 22nm. The screening phenomenon of the depletion region leads to better control of the channel by substrate and is the key to enhanced substrate bias effect in EδDC transistor. The variations of leakage power dissipation and intrinsic delay with substrate bias have been compared for EδDC and UDC transistor. Significant amount of leakage power saving is achieved in EδDC transistor in comparison to UDC transistor, at the cost of reduced intrinsic speed. The dependence of the substrate sensitivity of the EδDC transistor on the epitxial region thickness and concentration of the high doped screening region has been investigated.