18th International Symposium on VLSI Design and Test最新文献_第4页

Timing-driven Steiner tree construction on uniform λ-geometry 均匀λ几何上的定时驱动Steiner树构造

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881082

Radhamanjari Samanta, A. Erzin, S. Raha

引用次数: 2

An efficient hardware architecture for stereo disparity estimation 一种高效的立体视差估计硬件架构

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881049

Fradaric Joseph, Kiran Francis, Archita Hore, Siddhanta Roy, S. Josephine, R. Paily

引用次数: 1

FPGA-based real-time object tracker using modified particle filtering and SAD computation 基于改进粒子滤波和SAD计算的fpga实时目标跟踪器

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881045

Sanjay Singh, Ravi Saini, Sumeet Saurav, Anil K. Saini, C. Shekhar, Anil Vohra

引用次数: 2

A re-router for optimizing wire length in two-and four-layer no-dogleg channel routing 用于优化两层和四层无狗腿通道路由中的导线长度的重路由器

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881057

S. S. Sau, R. Pal

引用次数: 3

Design of a new high order OTA-C filter structure and its specification based testing 基于测试的新型高阶OTA-C滤波器结构设计及其规格

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881074

K. Ghosh, B. Ray

{"title":"Design of a new high order OTA-C filter structure and its specification based testing","authors":"K. Ghosh, B. Ray","doi":"10.1109/ISVDAT.2014.6881074","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881074","url":null,"abstract":"This paper presents a new higher order current mode filter structure based on Operational transconductance amplifier and capacitor (OTA-C). The structure fulfils the three main criteria of high frequency operation: (i) It employs minimum number of active and passive components (ii) It employs only single ended input OTAs to overcome feedthrough effects. (iii) It uses only grounded capacitor which is useful for integration and absorb shunt capacitance. Any nth order transfer function can be realised from it. Fourth order low pass elliptic filter is designed and simulated. HSPICE simulation with BSIM level 53 model and 0.13 μm process confirm the theoretical analysis. The second part of the paper proposes a new method of specification based parametric fault detection of higher order linear analog circuit where a number of test nodes are accessible. The method is illustrated with designed fourth order low pass elliptic filter. Current gains at different stage of the filter are used for fault detection. Using montecarlo simulation the value of each component of the circuit is varied within its tolerance limit and minimum and maximum values of the each current gain are found for the fault free circuit. At the time of testing, the current gains are found for the injected fault and if any one or more current gain are found out of bound then the circuit is faulty. Numerical results are presented to clarify the proposed method and to prove its efficiency.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131739454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Pipelined FFT architectures for real-time signal processing and wireless communication applications 用于实时信号处理和无线通信应用的流水线FFT架构

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881052

A. X. Glittas, G. Lakshminarayanan

引用次数: 10

TID effects on retention of 0.13 μm SONOS memory cell: A device simulation approach TID对0.13 μm SONOS记忆单元保留率的影响:器件模拟方法

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881090

Shipra Bassi, M. Pattanaik

引用次数: 4

Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers 通过使用SMT求解器增加基于路径的等价检查器来扩展翻译验证的范围

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881061

K. Banerjee, C. Mandal, D. Sarkar

{"title":"Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers","authors":"K. Banerjee, C. Mandal, D. Sarkar","doi":"10.1109/ISVDAT.2014.6881061","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881061","url":null,"abstract":"The initial behavioural specification of an embedded system goes through significant optimizing transformations, automated and also human guided, before being mapped to an architecture. Establishing the validity of these transformations is crucial to ensure that the intended behaviour of a system has not been faultily altered during synthesis. Finite state machines with datapath (FSMDs) have traditionally been used to model the specification and the implementation. Path based equivalence checkers over this model have been proposed to validate the translation process. Since specification for digital systems implementing algorithmic computations over integers involves the whole of integer arithmetic which is undecidable, majority of these equivalence checkers employ a normalization technique that tries to reduce two computationally equivalent expressions e1 and e2 to a syntactically identical form. This normalization technique, however, is not applicable to reason over finite precision datatypes. In this work, we propose to augment the normalization module, wherever necessary, with an SMT solver to determine the validity of e1= e2. The scope of translation validation can be extended to handle bit-vectors, user-defined datatypes and more sophisticated transformations by leveraging the capability of SMT solvers while keeping the basic equivalence checking framework intact. We have explored three state-of-the-art SMT solvers namely, Yices2, CVC4 and Z3. The experiments demonstrate improvement in terms of its scope of application over the existing methodology.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"52 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133239278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Architectures and algorithms for image and video processing using FPGA-based platform 基于fpga平台的图像和视频处理体系结构和算法

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881081

J. Pandey, Arindam Karmakar, S. Gurunarayanan

引用次数: 5

Automatic real-time extraction of focused regions in a live video stream using edge width information 利用边缘宽度信息在实时视频流中自动实时提取聚焦区域

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881046

Sanjay Singh, Sumeet Saurav, Ravi Saini, Anil K. Saini, C. Shekhar, Anil Vohra

引用次数: 1