18th International Symposium on VLSI Design and Test最新文献_第3页

Power optimized PLL implementation in 180nm CMOS technology 功率优化锁相环实现在180nm CMOS技术

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881065

S. Patri, P. Devulapalli, Dhananjay Kewale, Omkar Asbe, K. Prasad

引用次数: 10

Cryptanalysis of Composite PUFs (Extended abstract-invited talk) 复合puf的密码分析(扩展摘要-邀请讲座)

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881035

Phuong Ha Nguyen, D. Sahoo, Debdeep Mukhopadhyay, R. Chakraborty

引用次数: 4

A novel architecture for QPSK modulation based on time-mode signal processing 一种基于时模信号处理的QPSK调制新架构

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881056

S. Saha, B. Kar, S. Sur-Kolay

{"title":"A novel architecture for QPSK modulation based on time-mode signal processing","authors":"S. Saha, B. Kar, S. Sur-Kolay","doi":"10.1109/ISVDAT.2014.6881056","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881056","url":null,"abstract":"With shrinking process technology, the scale of integration has increased significantly for digital design. Therefore, the increase in operating frequency, and attempt to reduce area and power has been addressed to large extent. On the contrary, it has lesser impact on its analog counterpart and has not been able to catch up with the respective design metrics pertaining to digital design. This paper presents a new design method for Quadrature Phase Shift Keying (QPSK) modulation technique using Time Mode Signal Processing (TMSP) technique. This method uses a digital clock signal acting as the carrier signal and thus provides a digital interface at the output. A 2 bit input digital code modulates the delay of the clock and hence carries the information in it. The proposed design yields a low voltage and low power alternative to its known analog counterparts. We implemented the design using 0.18μm TSMC CMOS technology. The power supply is kept at 2V, while the carrier frequency remains 250MHz. The results for both pre and post-layout simulations yield significant improvement in layout area, power dissipation and signal-to-noise ratio (SNR) as compared to a conventional design for QPSK modulation.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124380197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip 一种新的三维片上网络递归分区组播路由算法

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881040

Narendra Kumar Meena, H. Kapoor, Shounak Chakraborty

引用次数: 7

A positive level shifter for high speed symmetric switching in flash memories 用于快闪存储器中高速对称开关的正电平移位器

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881064

Rohan Sinha, M. Hashmi, G. Kumar

引用次数: 3

An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect 考虑井邻近效应的大尺度CMOS逆变器经验delta延迟模型

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881062

Bijay Kumar Dalai, N. Karnnan, A. Sharma, B. Anand

引用次数: 0

An analytic potential and threshold voltage model for short-channel symmetric double-gate MOSFET 短沟道对称双栅MOSFET的解析电位和阈值电压模型

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881048

V. Yadav, R. K. Baruah

引用次数: 4

VLSI design of fast fractal image encoder 快速分形图像编码器的VLSI设计

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881071

M. Panigrahy, I. Chakrabarti, A. Dhar

引用次数: 6

Hardware accelerator for real-time image resizing 用于实时图像调整大小的硬件加速器

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881070

Pranav Narayan Gour, S. Narumanchi, Sumeet Saurav, Sanjay Singh

{"title":"Hardware accelerator for real-time image resizing","authors":"Pranav Narayan Gour, S. Narumanchi, Sumeet Saurav, Sanjay Singh","doi":"10.1109/ISVDAT.2014.6881070","DOIUrl":"https://doi.org/10.1109/ISVDAT.2014.6881070","url":null,"abstract":"An accurate, hardware efficient and fast image rescaling unit is a crucial part of any real-time image processing system. Although there are a number of image scaling algorithms existing in the literature but Bicubic and Bilinear interpolation algorithms are most widely used. In the recent years, numerous algorithms have been proposed that aim to bridge the gap between these two standard algorithms, by attempting to provide high image quality of the former while maintaining the computational simplicity of the latter. This paper proposes a novel image resizing algorithm which uses a four-part piecewise linear function that closely mimics the behavior of the bicubic kernel, and thus provides high quality resized images comparable to Bicubic interpolation while having a much lower computational cost. An optimized architecture is proposed to implement this algorithm which features a high re-use of hardware units for coefficient generation so that the hardware cost is comparable to that of bilinear interpolation. The architecture and algorithm have been designed in tandem so as to meet the real-time requirements of applications such as automated video surveillance, requiring minimal hardware use without compromising on image quality.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121304686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Operation-aware assist circuit design for improved write performance of FinFET based SRAM 改进基于FinFET的SRAM写入性能的操作感知辅助电路设计

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI: 10.1109/ISVDAT.2014.6881063

Ekta Prajapati, N. Yadav, M. Pattanaik, G. K. Sharma

引用次数: 0