An analytical delay model for CMOS Inverter-Transmission Gate structure

Mohammad Shueb Romi, N. Alam, M. Y. Yasin
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引用次数: 5

Abstract

This paper presents a novel approach for delay modeling of Inverter followed by Transmission Gate (Inv-TG) structure. Our model is novel in the sense that it considers the series stack effect along with the internal node voltage and parasitic capacitance while treating the Inv-TG structure as a single entity. Subsequently, we propose a methodology to incorporate the effect of Process-Voltage-Temperature (PVT) variations in the derived model. We compare our derived model against the SPICE simulation results using 32nm Predictive Technology Model. We observe that the error in the estimated delay using our model is within the acceptable range (<;10%).
CMOS逆变-传输门结构的解析延迟模型
提出了一种基于传输门(Inv-TG)结构的逆变器延迟建模新方法。我们的模型是新颖的,因为它考虑了串联堆叠效应以及内部节点电压和寄生电容,同时将Inv-TG结构视为单个实体。随后,我们提出了一种将过程电压温度(PVT)变化的影响纳入推导模型的方法。我们将导出的模型与使用32nm预测技术模型的SPICE仿真结果进行了比较。我们观察到,使用我们的模型估计延迟的误差在可接受的范围内(<;10%)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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