An analytical delay model for CMOS Inverter-Transmission Gate structure

Abstract

This paper presents a novel approach for delay modeling of Inverter followed by Transmission Gate (Inv-TG) structure. Our model is novel in the sense that it considers the series stack effect along with the internal node voltage and parasitic capacitance while treating the Inv-TG structure as a single entity. Subsequently, we propose a methodology to incorporate the effect of Process-Voltage-Temperature (PVT) variations in the derived model. We compare our derived model against the SPICE simulation results using 32nm Predictive Technology Model. We observe that the error in the estimated delay using our model is within the acceptable range (<;10%).