{"title":"High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications","authors":"Dilsukh Nehra, P. Pal, B. Kaushik, S. Dasgupta","doi":"10.1109/ISVDAT.2014.6881054","DOIUrl":null,"url":null,"abstract":"In this paper, we present the impact of spacer dielectric on a junctionless transistor (JLT) FinFET based circuit/SRAM memory cell. JLT FinFETs with high-k spacers provide excellent electrostatic integrity as well as reduction in short channel effects (SCEs). Fringing electric field through spacer increases effective channel length in the OFF-state, whereas in ON-state it is unaffected. It is observed that the drive current, leakage current, drain induced barrier lowering (DIBL) and sub-threshold swing (SS) are improved. The JLT structure with spacers leads to better noise-margins of CMOS inverter. Moreover, the JLT architecture also improves the performance of SRAM in terms of static-noise margins (SNMs) and leakage power with increase in high-k spacer value. High-k spacer increase the capacitance of the device, so ring oscillator delay and SRAM access times are degraded.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"18th International Symposium on VLSI Design and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVDAT.2014.6881054","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, we present the impact of spacer dielectric on a junctionless transistor (JLT) FinFET based circuit/SRAM memory cell. JLT FinFETs with high-k spacers provide excellent electrostatic integrity as well as reduction in short channel effects (SCEs). Fringing electric field through spacer increases effective channel length in the OFF-state, whereas in ON-state it is unaffected. It is observed that the drive current, leakage current, drain induced barrier lowering (DIBL) and sub-threshold swing (SS) are improved. The JLT structure with spacers leads to better noise-margins of CMOS inverter. Moreover, the JLT architecture also improves the performance of SRAM in terms of static-noise margins (SNMs) and leakage power with increase in high-k spacer value. High-k spacer increase the capacitance of the device, so ring oscillator delay and SRAM access times are degraded.