High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications

Dilsukh Nehra, P. Pal, B. Kaushik, S. Dasgupta
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引用次数: 3

Abstract

In this paper, we present the impact of spacer dielectric on a junctionless transistor (JLT) FinFET based circuit/SRAM memory cell. JLT FinFETs with high-k spacers provide excellent electrostatic integrity as well as reduction in short channel effects (SCEs). Fringing electric field through spacer increases effective channel length in the OFF-state, whereas in ON-state it is unaffected. It is observed that the drive current, leakage current, drain induced barrier lowering (DIBL) and sub-threshold swing (SS) are improved. The JLT structure with spacers leads to better noise-margins of CMOS inverter. Moreover, the JLT architecture also improves the performance of SRAM in terms of static-noise margins (SNMs) and leakage power with increase in high-k spacer value. High-k spacer increase the capacitance of the device, so ring oscillator delay and SRAM access times are degraded.
基于无结FinFET的电路/SRAM应用中的高介电常数间隔效应
在本文中,我们提出了间隔介质对基于无结晶体管(JLT) FinFET的电路/SRAM存储单元的影响。具有高k间隔的JLT finfet提供出色的静电完整性以及减少短通道效应(SCEs)。在关闭状态下,通过间隔片的边缘电场增加了有效沟道长度,而在打开状态下则不受影响。结果表明,驱动电流、漏电流、漏极势垒降低(DIBL)和亚阈值摆幅(SS)得到改善。带间隔的JLT结构使CMOS逆变器具有更好的噪声裕度。此外,随着高k间隔值的增加,JLT架构在静态噪声裕度(SNMs)和泄漏功率方面也提高了SRAM的性能。高k间隔增加了器件的电容,因此降低了环形振荡器的延迟和SRAM的访问时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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