A BDD based secure hardware design method to guard against power analysis attacks

Abstract

Power analysis attacks (PAAs) present a major threat towards safeguarding the secrets of cryptographic systems. We have devised a hardware countermeasure in the form of a Binary Decision Diagram (BDD) based dual-rail circuits and a supporting synthesis procedure. We have, for the first time, used the BDD to model the pre-charge generation logic while designing such a cell. Experimental results demonstrate the resistance against power analysis attacks of circuits developed using this approach, while outperforming other contemporary designs in terms of peak power variance, average power and average current. All results have been obtained using 65nm technology.