超低功耗应用中采用单时钟节能绝热逻辑的顺序电路设计

18th International Symposium on VLSI Design and Test Pub Date : 2014-07-16 DOI:10.1109/ISVDAT.2014.6881076

M. Chanda, A. S. Chakraborty, S. Nag, Raina Modak

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引用次数: 10

摘要

提出了一种基于节能绝热逻辑(EEAL)的节能可调绝热顺序电路。绝热触发器和顺序电路已在TSMC 0.18 μm CMOS技术上采用EEAL方式实现。大量的CADENCE仿真表明，基于EEAL的顺序电路消耗的总能量仅为其他命令式逻辑风格的22%-35%。

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Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application

This paper presents energy efficient pre-settable adiabatic sequential circuits based on the Energy efficient adiabatic Logic (EEAL). Adiabatic Flip-flops and sequential circuits have been implemented using EEAL style in a TSMC 0.18 μm CMOS technology. Extensive CADENCE simulations show that EEAL based sequential circuit consumes only 22%-35% of total energy consumed by others imperative logic styles.

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18th International Symposium on VLSI Design and Test

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