{"title":"超低功耗应用中采用单时钟节能绝热逻辑的顺序电路设计","authors":"M. Chanda, A. S. Chakraborty, S. Nag, Raina Modak","doi":"10.1109/ISVDAT.2014.6881076","DOIUrl":null,"url":null,"abstract":"This paper presents energy efficient pre-settable adiabatic sequential circuits based on the Energy efficient adiabatic Logic (EEAL). Adiabatic Flip-flops and sequential circuits have been implemented using EEAL style in a TSMC 0.18 μm CMOS technology. Extensive CADENCE simulations show that EEAL based sequential circuit consumes only 22%-35% of total energy consumed by others imperative logic styles.","PeriodicalId":217280,"journal":{"name":"18th International Symposium on VLSI Design and Test","volume":"322 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application\",\"authors\":\"M. Chanda, A. S. Chakraborty, S. Nag, Raina Modak\",\"doi\":\"10.1109/ISVDAT.2014.6881076\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents energy efficient pre-settable adiabatic sequential circuits based on the Energy efficient adiabatic Logic (EEAL). Adiabatic Flip-flops and sequential circuits have been implemented using EEAL style in a TSMC 0.18 μm CMOS technology. Extensive CADENCE simulations show that EEAL based sequential circuit consumes only 22%-35% of total energy consumed by others imperative logic styles.\",\"PeriodicalId\":217280,\"journal\":{\"name\":\"18th International Symposium on VLSI Design and Test\",\"volume\":\"322 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-07-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"18th International Symposium on VLSI Design and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVDAT.2014.6881076\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"18th International Symposium on VLSI Design and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVDAT.2014.6881076","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application
This paper presents energy efficient pre-settable adiabatic sequential circuits based on the Energy efficient adiabatic Logic (EEAL). Adiabatic Flip-flops and sequential circuits have been implemented using EEAL style in a TSMC 0.18 μm CMOS technology. Extensive CADENCE simulations show that EEAL based sequential circuit consumes only 22%-35% of total energy consumed by others imperative logic styles.