Russian Microelectronics最新文献_第10页

Erratum to: Design of a Nonlinear Model of a Pseudomorphic 0.15 µm рHEMT AlGaAs/InGaAs/GaAs Transistor 勘误：设计一个伪态 0.15 µm рHEMT AlGaAs/InGaAs/GaAs 晶体管的非线性模型

Russian Microelectronics Pub Date : 2024-02-08 DOI: 10.1134/s1063739723900043

D. Tsunvaza, R. V. Ryzhuk, I. S. Vasil’evskii, N. I. Kargin, V. A. Klokov

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Probe and Spectral Diagnostics of the Plasma of the BCl3–Cl2 Gas Medium BCl3-Cl2 气体介质等离子体的探针和光谱诊断法

Russian Microelectronics Pub Date : 2024-02-08 DOI: 10.1134/s1063739723700701

D. B. Murin, I. A. Chesnokov, I. A. Gogulev, A. E. Grishkov

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Optically Pumped Bipolar Transistor 光泵双极晶体管

Russian Microelectronics Pub Date : 2024-02-08 DOI: 10.1134/s1063739723700762

Yu. K. Al’tudov, D. S. Gaev, A. V. Pskhu, S. Sh. Rekhviashvili

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Design of Integrated Voltage Multipliers Using Standard CMOS Technologies 利用标准 CMOS 技术设计集成电压倍增器

Russian Microelectronics Pub Date : 2024-02-08 DOI: 10.1134/s1063739723700713

A. S. Sinyukin, B. G. Konoplev, A. V. Kovalev

{"title":"Design of Integrated Voltage Multipliers Using Standard CMOS Technologies","authors":"A. S. Sinyukin, B. G. Konoplev, A. V. Kovalev","doi":"10.1134/s1063739723700713","DOIUrl":"https://doi.org/10.1134/s1063739723700713","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>The results of the design of integrated multistage voltage multipliers as components of supply modules for wireless passive microdevices are presented. The parameters of transistors that are significant for the construction of multipliers are considered for three typical CMOS technologies: CM018G 180 nm, HCMOS8D 180 nm, and C250G 250 nm. The Cadence CAD simulation results demonstrate that when implementing an eight-stage multiplier using the CM018G technology, the minimum output voltage level required for operation of the microcircuit is achieved at input amplitude of 250 mV; and when implementing a similar device using the HCMOS8D technology, at an amplitude of 375 mV. Using the example of the constructed 16-stage multiplier, it is shown that the voltage multiplication efficiency values range from 20 to 54% for a wide range of the input voltage, and the efficiency decreases only by 1–3% compared to the 8-stage implementation. The proposed recommendations for the design of integrated voltage rectifiers-multipliers can be used in the development of the passive supply units for microelectronic devices.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"10 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139771040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Performance Calculation for a MEMS Switch with a Floating Electrode 带浮动电极的微机电系统开关的性能计算

Russian Microelectronics Pub Date : 2024-02-08 DOI: 10.1134/s1063739723700750

M. O. Morozov, I. V. Uvarov

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Tapered Silicon Oxide Etching for Creation of Capacitor Structures for Measurement of Dielectric Characteristics 锥形氧化硅蚀刻用于创建电容器结构以测量介电特性

Russian Microelectronics Pub Date : 2024-02-08 DOI: 10.1134/s1063739723700695

A. V. Miakonkikh, V. O. Kuzmenko, A. E. Melnikov, K. V. Rudenko

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Performance Estimation and Application of Analog Device using 32 nm CNFET 使用 32 纳米 CNFET 的模拟设备的性能评估与应用

Russian Microelectronics Pub Date : 2024-02-08 DOI: 10.1134/s1063739723700683

S. K. Tripathi, Raju Patel, Deepak Agrawal, Manoj Singh Adhikari

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Prototypes of Devices for Heterogeneous Hybrid Semiconductor Electronics with an Embedded Biomolecular Domain 嵌入生物分子域的异质混合半导体电子器件原型

Russian Microelectronics Pub Date : 2024-02-08 DOI: 10.1134/s1063739723700725

M. A. Baranov, E. K. Karseeva, O. Yu. Tsybin

{"title":"Prototypes of Devices for Heterogeneous Hybrid Semiconductor Electronics with an Embedded Biomolecular Domain","authors":"M. A. Baranov, E. K. Karseeva, O. Yu. Tsybin","doi":"10.1134/s1063739723700725","DOIUrl":"https://doi.org/10.1134/s1063739723700725","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>A macromolecular system embedded in a semiconductor microelectronic device is considered as a biomolecular nano- or micro-sized domain that performs the functions of converting acoustic and electromagnetic signals. The issues of the choice of substances, the dynamic and structural-functional state of the domain, and the physical foundations of its interaction with matrix elements are discussed. The process of excitation of forced oscillations in amino acid molecules (for example, glycine, tryptophan, and diphenyl-L-alanine) under the influence of short (10–100 ps) packets of electrical signals in the IR range with a frequency in the range of 1–125 THz is studied by the method of supercomputer nonequilibrium modeling of molecular dynamics. The acoustoelectric interpretation of oscillation generation is carried out using a unified equivalent circuit of the peptide group. Examples of prototypes of heterogeneous devices being developed are given. It is concluded that embedded biomolecular domains, presented as a multifunctional element base, are promising for signal conversion in hybrid microelectronics.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"8 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139760457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Simulation of a Vertical Ballistic Quantum-Barrier Field-Effect Transistor Based on an Undoped AlxGa1–xAs Quantum Nanowire 模拟基于未掺杂 AlxGa1-xAs 量子纳米线的垂直弹道量子势垒场效应晶体管

Russian Microelectronics Pub Date : 2024-02-08 DOI: 10.1134/s1063739723700749

D. V. Pozdnyakov, A. V. Borzdov, V. M. Borzdov

{"title":"Simulation of a Vertical Ballistic Quantum-Barrier Field-Effect Transistor Based on an Undoped AlxGa1–xAs Quantum Nanowire","authors":"D. V. Pozdnyakov, A. V. Borzdov, V. M. Borzdov","doi":"10.1134/s1063739723700749","DOIUrl":"https://doi.org/10.1134/s1063739723700749","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>A design and topological solution for a tunnel field-effect transistor of a new type is proposed and the simulation of the transistor is performed. The device is a vertical ballistic field-effect transistor with a cylindrical metallic gate based on a cylindrical undoped Al<sub><i>x</i></sub>Ga<sub>1–<i>x</i></sub>As quantum nanowire located in an Al<sub>2</sub>O<sub>3</sub> matrix. For the given geometry of the device structure, the optimum of the fraction of aluminum in the semiconductor composition varying along the transistor channel is found, at which, unlike a conventional tunnel field-effect transistor, not only is the complete suppression of the quantum barrier for electrons by a positive gate voltage ensured but also the minimum possible electrical resistance of the transistor channel is achieved. The current-voltage characteristics of the transistor are calculated within the framework of a rigorous quantum-mechanical description of the electron transport in its channel, taking into account the nonparabolic nature of the band structure of the semiconductor.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"5 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139760346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Evaluation of Low Power CMOS Based Schmitt Trigger Circuits 基于施密特触发器的低功耗 CMOS 电路的设计与评估

Russian Microelectronics Pub Date : 2023-12-01 DOI: 10.1134/s1063739723700671

{"title":"Design and Evaluation of Low Power CMOS Based Schmitt Trigger Circuits","authors":"","doi":"10.1134/s1063739723700671","DOIUrl":"https://doi.org/10.1134/s1063739723700671","url":null,"abstract":"<span> <h3>Abstract</h3> <p>The requirement of high speed low power square wave generators that yield spike free signal enabled the design of Schmitt trigger circuit. The designs BJT or FET based circuits have disadvantages like spikes in output signal cannot be suppressed, the output signal gain control is required, low packing density, considerable power dissipation, etc. This has paved way to development of CMOS based design. Further low power requirement enabled the CMOS based low power design aspects for the Schmitt trigger circuit. The designs are modeled in DSCH and Microwind tools for schematic and layout development at various technologies like 90, 65, 45, 32 and 22 nm. The choice of designs used are basic Schmitt trigger circuit, dynamic CMOS logic based Schmitt trigger circuit, pseudo NMOS based Schmitt trigger circuit, weak PMOS domino based Schmitt trigger circuit, NORA logic based Schmitt trigger circuit, leakage control transistor (LECTOR) based Schmitt trigger circuit, GALEOR (gated leakage transistor) based Schmitt trigger circuit and feed-forward leakage self-suppression logic (FFLSSL) based Schmitt trigger circuit. While the least number of transistors used are in the pseudo NMOS based Schmitt trigger circuit and highest number of transistors are used in NORA logic based Schmitt trigger circuit. Still pseudo NMOS requires ratioed logic which is a measure drawback. The pseudo NMOS logic based Schmitt trigger circuit occupies very less area by at least 27.027%. The power dissipation is very less in FFLSSL based Schmitt Trigger circuit by at least 75%. The delay is less in FFLSSL based Schmitt trigger circuit by at least 10.15%.</p> </span>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"19 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139760476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0