Design and Evaluation of Low Power CMOS Based Schmitt Trigger Circuits

Abstract

The requirement of high speed low power square wave generators that yield spike free signal enabled the design of Schmitt trigger circuit. The designs BJT or FET based circuits have disadvantages like spikes in output signal cannot be suppressed, the output signal gain control is required, low packing density, considerable power dissipation, etc. This has paved way to development of CMOS based design. Further low power requirement enabled the CMOS based low power design aspects for the Schmitt trigger circuit. The designs are modeled in DSCH and Microwind tools for schematic and layout development at various technologies like 90, 65, 45, 32 and 22 nm. The choice of designs used are basic Schmitt trigger circuit, dynamic CMOS logic based Schmitt trigger circuit, pseudo NMOS based Schmitt trigger circuit, weak PMOS domino based Schmitt trigger circuit, NORA logic based Schmitt trigger circuit, leakage control transistor (LECTOR) based Schmitt trigger circuit, GALEOR (gated leakage transistor) based Schmitt trigger circuit and feed-forward leakage self-suppression logic (FFLSSL) based Schmitt trigger circuit. While the least number of transistors used are in the pseudo NMOS based Schmitt trigger circuit and highest number of transistors are used in NORA logic based Schmitt trigger circuit. Still pseudo NMOS requires ratioed logic which is a measure drawback. The pseudo NMOS logic based Schmitt trigger circuit occupies very less area by at least 27.027%. The power dissipation is very less in FFLSSL based Schmitt Trigger circuit by at least 75%. The delay is less in FFLSSL based Schmitt trigger circuit by at least 10.15%.