{"title":"Thermal Modeling and Layout Optimization of GaN Half-Bridge IC with Integrated Drivers and Power HEMTs","authors":"V. A. Kagadey, I. Y. Kodorova, E. S. Polyntsev","doi":"10.1134/s1063739724600225","DOIUrl":"https://doi.org/10.1134/s1063739724600225","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"69 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141777991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Deepak Agrawal, Shailendra K. Tripathi, N Soma Sekhar Reddy, M. Sai Vineeth Reddy, P. Mohammad Shoaib
{"title":"Design a Configurable First Order Universal Filter Using a Single EX-CCCII","authors":"Deepak Agrawal, Shailendra K. Tripathi, N Soma Sekhar Reddy, M. Sai Vineeth Reddy, P. Mohammad Shoaib","doi":"10.1134/s1063739724600080","DOIUrl":"https://doi.org/10.1134/s1063739724600080","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>In this work, a single active element (Extra-X Current Controlled Conveyor) with grounded capacitor is used to design a reconfigurable first-order universal filter (CFUF). By simply swapping the digital control words (<i>k</i><sub>1</sub><i>k</i><sub>2</sub>), the suggested circuit may implement all of the common filter responses, including high-pass, low-pass, and all-pass. An EX-CCCII serves as the active element in the filter setup, which is based on a novel topology, which provides several advantages, such as reduced complexity, low power consumption, and improved performance. The following advantages of the proposed circuit: high input impedance for voltage input signals, electronically controllable pole frequency that varies with bias current, and a single grounded capacitor that can be integrated into an IC. At a power supply level of ±0.5 V, the proposed circuit is modeled using specifications for 0.18-micrometer CMOS technology. PSPICE simulation tool is used to demonstrate the filter’s performance.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"28 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141777990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Influence of Laser Radiation on Functional Properties MOS Device Structures","authors":"S. Sh. Rekhviashvili, D. S. Gaev","doi":"10.1134/s1063739724600262","DOIUrl":"https://doi.org/10.1134/s1063739724600262","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>The electrical and physical properties of MOS device structures (capacitor, field-effect transistor with an insulated gate and induced channel, CMOS integrated circuit) when exposed to unmodulated laser radiation are studied. The static and dynamic characteristics are measured. The theoretical study is carried out using the developed SPICE models and numerical experiments. An expression is obtained for the volt-ampere characteristics (VACs) of a field-effect transistor operating in a mode with constant optical illumination. It is shown that the characteristics of structures are determined by the generation and recombination of nonequilibrium charge carriers, the field effect, and the photovoltaic effect in <i>p–n</i>-junctions, the Dember effect, and the tunneling of charge carriers through the gate dielectric. The results of the study are of interest in terms of creating high-speed transistors and integrated circuits of a new type.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"376 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141777985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. S. Gusev, A. O. Sultanov, A. V. Katkov, S. M. Ryndya, N. V. Siglovaya, A. N. Klochkov, R. V. Ryzhuk, N. I. Kargin, D. P. Borisenko
{"title":"Analysis of Carrier Scattering Mechanisms in AlN/GaN HEMT Heterostructures with an Ultrathin AlN Barrier","authors":"A. S. Gusev, A. O. Sultanov, A. V. Katkov, S. M. Ryndya, N. V. Siglovaya, A. N. Klochkov, R. V. Ryzhuk, N. I. Kargin, D. P. Borisenko","doi":"10.1134/s1063739724600304","DOIUrl":"https://doi.org/10.1134/s1063739724600304","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>Using the method of molecular beam epitaxy with the plasma activation of nitrogen, experimental AlN/GaN heterostructures (HSs) with an ultrathin AlN barrier are obtained<i>.</i> The layer resistance of the optimized structures is less than 230 Ω/□. The scattering processes that limit the mobility of a two-dimensional electron gas (2DEG) in undoped AlN/GaN HSs with an ultrathin AlN barrier are studied. It is shown that in the range of <i>n</i><sub><i>s</i></sub> characteristic for AlN/GaN HEMT HSs (<i>n</i><sub>s</sub> > 1 × 10<sup>13</sup> cm<sup>–2</sup>), a noticeable contribution to the scattering of charge carriers is made by the roughness of the heterointerface.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"245 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141777988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"How Memristor Device Records Memory Signal: Electromagnetic Study through an Equivalent Setup","authors":"Hassan Ali","doi":"10.1134/s1063739724600043","DOIUrl":"https://doi.org/10.1134/s1063739724600043","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>Memristor is an electronic device, which corresponds to a switch translating memory data (synapse) into resistance values. Scientists made a switch with a combination of titanium dioxide (Tio<sub>2</sub>) and oxygen deficient TiO<sub>2</sub> to create a metal-insulator transition mechanism to make a device with nonlinear conductive states <i>R</i><sub>on</sub> and <i>R</i><sub>off</sub>. This work presents the memory storing capability of memristor by utilizing an equivalent experimental setup of steel balls array. An experiment exhibits an identical memristive mechanism of memristor device where the nonlinear conductive states along an array of steel balls describes an exact mechanism of memristor’s functionality. Via utilizing an identical setup, we depict electric and magnetic field compatibility at memristor’s <i>pinched</i> (<sub>on & off</sub>) regions. It shows that how memristor stores synaptic information by means of resistance values at its <i>pinched</i> (<sub>on & off</sub>) conducting regions. The aim of this effort is to provide technical support to conceive a memristor as a resistive memory storage device, which changes its resistance values with respect to applied voltage (multiple synaptic weights).</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"57 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141785557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation of Silicon Field-Effect Conical GAA Nanotransistors with a Stacked SiO2/HfO2 Subgate Dielectric","authors":"N. V. Masal’skii","doi":"10.1134/s1063739724600274","DOIUrl":"https://doi.org/10.1134/s1063739724600274","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>The issues of modeling the electrical characteristics of a silicon conical field-effect gate-all-around (GAA) nanotransistor are discussed. An analytical model of the drain current of a transistor with a fully encompassing conical gate with a stacked subgate SiO<sub>2</sub>/HfO<sub>2</sub> oxide, taking into account the influence of the charge of the interfacial trap at the Si/SiO<sub>2</sub> interface, is developed. To model the potential distribution in a conical working area under the condition of a constant trap density, an analytical solution of the Poisson equation is obtained using the parabolic approximation method in the cylindrical coordinate system with the corresponding boundary conditions. The potential model is used to develop an expression for the drain current of a GAA nanotransistor with a stacked subgate oxide. The key electrical and physical characteristics are numerically studied depending on the density of the traps and the thickness of the SiO<sub>2</sub> and HfO<sub>2</sub> layers.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"17 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141777986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Structure and Formation of Superflash Nonvolatile Memory Cells","authors":"D. A. Abdullaev, E. V. Bobrova, R. A. Milovanov","doi":"10.1134/s1063739724600249","DOIUrl":"https://doi.org/10.1134/s1063739724600249","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>Split-gate embedded Flash memory technology has been around for decades and has become the standard application for a wide range of devices such as microcontrollers and smart cards. Among them, due to a number of advantages, SuperFlash (SF) produced by Silicon Storage Technology is the most widely used nonvolatile memory technology. In this paper, the results of a study of the structure of memory cells (MCs) are presented and the principle of their operation, as well as the main technological stages of the production process of forming transistor structures, is discussed.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"53 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141777984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. V. Kurbatov, A. S. Rudy, V. V. Naumov, A. A. Mironenko, O. V. Savenko, M. A. Smirnova, L. A. Mazaletsky, D. E. Pukhov
{"title":"A Comprehensive Study of Nonuniformity Properties of the LiCoO2 Thin-Film Cathode Fabricated by RF Sputtering","authors":"S. V. Kurbatov, A. S. Rudy, V. V. Naumov, A. A. Mironenko, O. V. Savenko, M. A. Smirnova, L. A. Mazaletsky, D. E. Pukhov","doi":"10.1134/s1063739724600250","DOIUrl":"https://doi.org/10.1134/s1063739724600250","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>The influence of nonuniformity properties of the LiCoO<sub>2</sub> cathode film deposited by magnetron sputtering on the capacity of all-solid-state thin-film lithium-ion batteries (ASSLIB) was studied. It was found that the film nonuniformity corresponds to the magnetron plasma density distribution and the angular distribution of sputtered particles. The capacity distribution of the ASSLIB with LiCoO<sub>2</sub> cathode depending on the distance to the substrate center was studied. The maximum capacity corresponded to the dense part of the toroidal region of the magnetron plasma. It was determined that the main causes of batteries capacity decline in the central part and on the edge of the substrate are the impurity phase of lithium cobaltate and the smaller thickness of the cathode layer, respectively.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"55 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141777983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Kinetics of Electromigration Mass Transfer in the Interface Elements of Micro- and Nanoelectronics Depending on the Strength of Thin-Film Connections","authors":"T. M. Makhviladze, M. E. Sarychev","doi":"10.1134/s1063739724600286","DOIUrl":"https://doi.org/10.1134/s1063739724600286","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>This study improves and expands the scope of application of the theoretical model previously proposed by the authors, which describes the relationship between the strength and electromigration (diffusion) properties of interfaces formed by connected materials. In the developed model, a linear relationship is established between the values of the work of reversible interface separation <span>({{W}_{a}})</span> and electromigration activation energy <span>({{H}_{{EM}}})</span> in the interface. Estimates are made and the coefficients of the resulting relation are compared with experiments studying electromigration in a copper conductor coated with a protective dielectric. Using also the model previously developed by the authors, which describes the dependence of the quantity <span>({{W}_{a}})</span> on the concentrations of nonequilibrium lattice defects presenting in the volumes of connected materials, a number of effects due to the influence of such defects on processes caused by electromigration are predicted and studied. This study shows that by introducing nonequilibrium lattice defects in the form of atomic interstitial or substitutional impurities into the volumes of the joined materials, we can effectively influence on the characteristics of the electromigration instability of the shape of the interlayer boundary. For interstitial impurities, quantitative analytical estimates of the impurity concentration required to significantly change (both increase and decrease) the characteristic growth time of the instability of the shape of an initially flat interface are performed.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"26 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141777989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. A. Alyabina, E. A. Arkhipova, Yu. N. Buzynin, S. A. Denisov, A. V. Zdoroveishchev, A. M. Titova, V. Yu. Chalkov, V. G. Shengurov
{"title":"Development of a Ge-MISFET Instrument Structure with an Induced p-Type Channel","authors":"N. A. Alyabina, E. A. Arkhipova, Yu. N. Buzynin, S. A. Denisov, A. V. Zdoroveishchev, A. M. Titova, V. Yu. Chalkov, V. G. Shengurov","doi":"10.1134/s1063739724600298","DOIUrl":"https://doi.org/10.1134/s1063739724600298","url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>The conditions for the growth of <i>n</i>-type Ge layers with the parameters required to create a Ge-MISFET with an induced <i>p</i>-type channel using the hot wire chemical vapor deposition (HW CVD) method are determined. The conditions for deposition using electron beam deposition and subsequent annealing of the subgate high-k dielectric ZrO<sub>2</sub>:Y<sub>2</sub>O<sub>3</sub> layers are optimized, allowing us to achieve a leakage current value of 5 × 10<sup>–6</sup> A/cm<sup>2</sup>. For the developed device structure, some parameters of the Ge-MISFET are calculated, such as the channel length, maximum voltage between the sink and source, and breakdown voltage.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"51 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141785556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}