Design of Integrated Voltage Multipliers Using Standard CMOS Technologies

Abstract

The results of the design of integrated multistage voltage multipliers as components of supply modules for wireless passive microdevices are presented. The parameters of transistors that are significant for the construction of multipliers are considered for three typical CMOS technologies: CM018G 180 nm, HCMOS8D 180 nm, and C250G 250 nm. The Cadence CAD simulation results demonstrate that when implementing an eight-stage multiplier using the CM018G technology, the minimum output voltage level required for operation of the microcircuit is achieved at input amplitude of 250 mV; and when implementing a similar device using the HCMOS8D technology, at an amplitude of 375 mV. Using the example of the constructed 16-stage multiplier, it is shown that the voltage multiplication efficiency values range from 20 to 54% for a wide range of the input voltage, and the efficiency decreases only by 1–3% compared to the 8-stage implementation. The proposed recommendations for the design of integrated voltage rectifiers-multipliers can be used in the development of the passive supply units for microelectronic devices.