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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems最新文献

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Fault detection in sequential circuits through functional testing 通过功能测试的顺序电路故障检测
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595779
G. Buonanno, F. Fummi, D. Sciuto
{"title":"Fault detection in sequential circuits through functional testing","authors":"G. Buonanno, F. Fummi, D. Sciuto","doi":"10.1109/DFTVS.1993.595779","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595779","url":null,"abstract":"The authors present a new functional test pattern generation algorithm for sequential architectures based on their finite state machine specification. The algorithm is based on a functional fault model. Each transition of the finite state machine is analyzed and state distinguishing sequences are adopted to observe their final state. Overlapping of test sequences is performed in order to reduce test length. Experimental results have shown the effectiveness of the test algorithm both at the functional level and at the gate level. The relations between synthesis, fault coverage and testing will be also determined.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116416312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Functional testing of linear circuits using transient response analysis 用瞬态响应分析进行线性电路的功能测试
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595825
D. Taylor, P. Evans, D. Marland
{"title":"Functional testing of linear circuits using transient response analysis","authors":"D. Taylor, P. Evans, D. Marland","doi":"10.1109/DFTVS.1993.595825","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595825","url":null,"abstract":"The impulse response of a linear circuit element contains enough information to functionally characterize that element. A numerical technique for the comparison of observed and expected (reference) transient responses is presented. The application of this technique results in an index, which is an absolute measure of device functionality, and real-time pass/fail limits are then set by simulating functional defects in the device under test and noting the magnitude of the indices generated. Comparisons of transient response test results with the results obtained from conventional test programs are presented for D/A converters.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124714826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Catastrophic defects oriented testability analysis of a class AB amplifier 面向突变缺陷的AB类放大器可测试性分析
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595828
M. Sachdev
{"title":"Catastrophic defects oriented testability analysis of a class AB amplifier","authors":"M. Sachdev","doi":"10.1109/DFTVS.1993.595828","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595828","url":null,"abstract":"Process defects have been recognized as one of the major contributors to the yield loss in CMOS integrated circuits. Any test philosophy without taking into consideration the probable processing defects is likely to compromise the quality of the tested devices. Owing to the specification oriented testing, analog devices frequently suffer from quality and reliability related issues. However, defect oriented testability analysis can be utilized to improve the quality of test methods and reduce the test costs. Furthermore, this analysis can provide inputs to the designer to improve the design robustness against the likely process defects. This methodology has been demonstrated with an example of a class AB amplifier.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125439700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A high speed Reed-Solomon encoder-decoder for fault tolerant solid state disks 用于容错固态磁盘的高速里德-所罗门编码器
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595613
G. Cardarilli, M. D. Zenzo, P. O. Pistilli, A. Salsano
{"title":"A high speed Reed-Solomon encoder-decoder for fault tolerant solid state disks","authors":"G. Cardarilli, M. D. Zenzo, P. O. Pistilli, A. Salsano","doi":"10.1109/DFTVS.1993.595613","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595613","url":null,"abstract":"Many applications actually require high performance, fault tolerant mass memories, which can be implemented using solid state devices. The high cost of semiconductor memories is a fundamental obstacle to the use of semiconductor devices instead of mechanical ones in mass storage memories. The use of faulty memories connected with an ECC VLSI circuit is proposed to overcome these problems. The authors present both a general purpose architecture which can be used as a transparent replacement of a normal hard disk and the coding-decoding circuit which uses the Reed-Solomon code for coding and an original modified error trapping technique for decoding. Using this algorithm it is possible to reach the high transfer rate necessary for high performance solid state disks (SSDs) and the requirements of fault tolerance needed to use faulty memories. The proposed decoding technique, patented, has been used by Texas Instruments in an on-the-shelf SSD.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130305019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Current testing viability in dynamic CMOS circuits 动态CMOS电路的当前测试可行性
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595792
M. Renovell, J. Figueras
{"title":"Current testing viability in dynamic CMOS circuits","authors":"M. Renovell, J. Figueras","doi":"10.1109/DFTVS.1993.595792","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595792","url":null,"abstract":"Current testing of dynamic CMOS integrated circuits with single phase clock is investigated. The analysis is performed on a single phase stage dynamic CMOS module in the presence of internal bridging defects of low resistance. These defects produce intermediate voltage levels which cause difficulties to the logic testing methods based on voltage level comparison. It is shown that current testing may be an effective complement to the usual logic methods. Theoretical bounds on the coverage of single internal bridges obtainable by current testing are given.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129552861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Probabilistic identification of critical components for circuit delays 电路延迟关键元件的概率辨识
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595801
D. Wessels, J. Muzio
{"title":"Probabilistic identification of critical components for circuit delays","authors":"D. Wessels, J. Muzio","doi":"10.1109/DFTVS.1993.595801","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595801","url":null,"abstract":"It is clear that defect fault tolerance must eventually be expanded to include tolerance of delay-inducing defects. A circuit operating near its optimal speed is particularly sensitive to delay increases caused by defects in components which lie on maximum length or near-maximum length true paths. For circuits with many long false paths the identification of key paths, and therefore key components, is a difficult problem. The authors use a randomized algorithm to quickly identify a circuit's optimal operating speed, and also the components in which delay defects are most likely to adversely affect circuit operation. Categorization of these components permits an optimal use of available resources in the introduction of delay defect tolerance.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129718070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design rules for CMOS self checking circuits with parametric faults in the functional block 功能块参数故障的CMOS自检电路设计规则
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595822
C. Metra, M. Favalli, P. Olivo, B. Riccò
{"title":"Design rules for CMOS self checking circuits with parametric faults in the functional block","authors":"C. Metra, M. Favalli, P. Olivo, B. Riccò","doi":"10.1109/DFTVS.1993.595822","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595822","url":null,"abstract":"The authors investigate the detection of parametric bridging and delay faults in the functional block of self checking circuits (SCCS). As far as these faults are concerned, classical definitions are shown to become ambiguous, because they are entirely based on logic considerations. Thus, new definitions are here proposed to take care of the analogic and dynamic effects of such faults and to ensure that they do not produce any problem at system level. Moreover, rules aimed at the design of self checking circuits with combinational functional blocks satisfying these conditions are proposed.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"29 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134224102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Experiments on bridging fault analysis and layout-level DFT for CMOS designs CMOS设计的桥接故障分析和布置图级DFT实验
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595718
A. P. Casimiro, M. Simoes, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira
{"title":"Experiments on bridging fault analysis and layout-level DFT for CMOS designs","authors":"A. P. Casimiro, M. Simoes, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira","doi":"10.1109/DFTVS.1993.595718","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595718","url":null,"abstract":"High quality test of complex, digital VLSI circuits require a realistic test preparation, i.e., the ability to derive test patterns to cover faults, originated by physical defects. The issues of guiding test pattern generation for a realistic gate-level fault model, and of introducing new strategies for testability enhancement, at layout level, are addressed. Experiments on standard cell digital designs show the gate-level, realistic bridging faults should be used as target faults for test preparation. Moreover, it is demonstrated that bridging faults involving fanout nodes exhibit a dominant effect on testability. Finally, it is shown that routing with testability constraints is rewarding, and that routing channels should be carefully designed for hard fault avoidance. To produce such results, a new set of tools has been developed, and is presented here.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123581098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
System level policies for fault tolerance issues in the FERMI project FERMI项目中容错问题的系统级策略
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595597
A. Dell'Acqua, M. Hansen, S. Inkinen, B. Lofstedt, J. Vanuxem, C. Svensson, J. Yuan, H. Hentzell, L. Buono, J. David, J. Genat, H. Lebbolo, O. LeDortz, P. Nayman, A. Savoy-Navarro, R. Zitoun, C. Alippi, L. Breveglieri, L. Dadda, V. Piuri, F. Salice, M. Sami, R. Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, U. Gatti, F. Maloberti, G. Torelli, P. Carlson, A. Kerek, G. Appelquist, S. Berglund, C. Bohm, M. Engström, N. Yamdagni, R. Sundblad, I. Höglund, S. Persson
{"title":"System level policies for fault tolerance issues in the FERMI project","authors":"A. Dell'Acqua, M. Hansen, S. Inkinen, B. Lofstedt, J. Vanuxem, C. Svensson, J. Yuan, H. Hentzell, L. Buono, J. David, J. Genat, H. Lebbolo, O. LeDortz, P. Nayman, A. Savoy-Navarro, R. Zitoun, C. Alippi, L. Breveglieri, L. Dadda, V. Piuri, F. Salice, M. Sami, R. Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, U. Gatti, F. Maloberti, G. Torelli, P. Carlson, A. Kerek, G. Appelquist, S. Berglund, C. Bohm, M. Engström, N. Yamdagni, R. Sundblad, I. Höglund, S. Persson","doi":"10.1109/DFTVS.1993.595597","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595597","url":null,"abstract":"The FERMI system, performing acquisition and DSP of calorimeter data in high energy collision experiments, planned at the LHC collider (CERN, Geneva, CH) is briefly overviewed. The system relies mainly upon the FERMI module, a dedicated VLSI multichip device performing most of the above functions, which is to be installed in large quantities (around 10/sup 5/) in the immediate neighborhood of the collider itself, requiring rad-hard features. The issues for a system which absolutely requires fault diagnosis and possibly fault tolerance are described, with regard to the FERMI module itself.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116841669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A probabilistic measurement for totally self-checking circuits 一种完全自检电路的概率测量方法
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595821
Jien-Chung Lo, E. Fujiwara
{"title":"A probabilistic measurement for totally self-checking circuits","authors":"Jien-Chung Lo, E. Fujiwara","doi":"10.1109/DFTVS.1993.595821","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595821","url":null,"abstract":"The authors propose a probabilistic measurement for totally self-checking (TSC) circuits. This measurement is analogous to reliability of fault-tolerant systems and is defined as the probability of achieving TSC goal (PATG). PATG surpasses the TSC definitions in determining the applicability of a circuit in a given application environment. For example, it is shown that an embedded TSC two-rail checker with two out of its four code word inputs unavailable gains a higher PATG than that in the ideal case. It is also demonstrated that the extension of PATG concept to strongly fault-secure (SFS) circuits and strongly code disjoint (SCD) checkers. The PATG can be used in product specification, analogous to reliability, and can give precise behavioral description on fault/error handling performance of TSC circuits. This is a crucial step toward the practical applications of TSC or CED circuits.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132790823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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