Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems最新文献_第2页

Use of a segmentation technique to analyze the variability of the yield of a mature CMOS SRAM 利用分割技术分析成熟CMOS SRAM产率的可变性

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595750

F. Duvivier, M. Rivier, B. Burtschy, J. Charlot

引用次数: 2

A highly testable 1-out-of-3 CMOS checker 一个高度可测试的1-out- 3 CMOS检查器

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595823

C. Metra, M. Favalli, P. Olivo, B. Riccò

引用次数: 10

On the reconfigurable operation of arrays with defects for image processing 图像处理中缺陷阵列的可重构操作

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595657

J. Salinas, F. Lombardi

引用次数: 3

A defect-tolerant design for WSI interconnection networks and its application to hypercube WSI互连网络容错设计及其在超立方体中的应用

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595652

Hideo Ito

引用次数: 3

Analysis and comparison of fault tolerant FSM architecture based on SEC codes 基于SEC代码的FSM容错体系结构分析与比较

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595604

R. Rochet, R. Leveugle, G. Saucier

引用次数: 17

Block implementation of fault-tolerant LMS adaptive FIR filters 块实现的容错LMS自适应FIR滤波器

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595607

Liang-Jin Lin, G. Redinbo

{"title":"Block implementation of fault-tolerant LMS adaptive FIR filters","authors":"Liang-Jin Lin, G. Redinbo","doi":"10.1109/DFTVS.1993.595607","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595607","url":null,"abstract":"Adaptive FIR filters are widely used in a variety of modern digital signal processing application, and with the advancement in VLSI technology, it is now feasible to build fairly complicated multiprocessor systems which can provide the necessary computational power required by some highly demanding real-time signal processing applications. The increased computational power of such systems also makes fault tolerance an even more important issue that needs to be addressed carefully, because a single hardware failure can easily render the whole compuational results useless. Algorithm-based fault tolerance (ABFT), recently developed as an effective high level fault-tolerant technique, employs, in addition to the normal outputs, parity numbers that are related to the outputs. These parities can be used to concurrently detect, and in some cases correct, errors caused by hardware failures. A highly efficient implementation of the encoding scheme based on the weighted checksum code is proposed. It is particularly suitable for block adaptive signal processing, and the computational efficiency of this method is compared with that of the more general weighted checksum code.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125430606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Does the floorplan of a chip affect its yield? 芯片的平面布局会影响其成品率吗?

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595754

Z. Koren, I. Koren

引用次数: 8

An interactive yield estimator as a VLSI CAD tool 作为VLSI CAD工具的交互式良率估计器

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595763

I. Wagner, I. Koren

引用次数: 4

Reduction of fault detection costs through testable design of sequential architectures with signal feedbacks 通过具有信号反馈的序列结构的可测试设计来降低故障检测成本

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595805

M. Bombana, G. Buonanno, P. Cavalloro, Fabrizio Ferrandi, D. Sciuto, G. Zaza

引用次数: 1

Realistic fault analysis of CMOS analog building blocks CMOS模拟模块的实际故障分析

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI: 10.1109/DFTVS.1993.595827

P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira

引用次数: 1