一个高度可测试的1-out- 3 CMOS检查器

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI:10.1109/DFTVS.1993.595823

C. Metra, M. Favalli, P. Olivo, B. Riccò

{"title":"一个高度可测试的1-out- 3 CMOS检查器","authors":"C. Metra, M. Favalli, P. Olivo, B. Riccò","doi":"10.1109/DFTVS.1993.595823","DOIUrl":null,"url":null,"abstract":"The problem of the design of a highly testable 1-out-of-3 CMOS checker has been considered. First some recently presented CMOS checkers have been analyzed, then a novel checker has been proposed to be certainly preferable from the self-testing capability and overall performance point of view.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A highly testable 1-out-of-3 CMOS checker\",\"authors\":\"C. Metra, M. Favalli, P. Olivo, B. Riccò\",\"doi\":\"10.1109/DFTVS.1993.595823\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The problem of the design of a highly testable 1-out-of-3 CMOS checker has been considered. First some recently presented CMOS checkers have been analyzed, then a novel checker has been proposed to be certainly preferable from the self-testing capability and overall performance point of view.\",\"PeriodicalId\":213798,\"journal\":{\"name\":\"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1993.595823\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1993.595823","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

考虑了高可测试性1-out- 3 CMOS检查器的设计问题。首先分析了最近出现的一些CMOS检查器，然后从自测试能力和整体性能的角度提出了一种新的检查器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A highly testable 1-out-of-3 CMOS checker

The problem of the design of a highly testable 1-out-of-3 CMOS checker has been considered. First some recently presented CMOS checkers have been analyzed, then a novel checker has been proposed to be certainly preferable from the self-testing capability and overall performance point of view.

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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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