Analysis and comparison of fault tolerant FSM architecture based on SEC codes

Abstract

Implementing single fault tolerant finite state machines (FSMs) in VLSI circuits might be done using triplication and voting (TMR). Alternatives are based on the use of an error correcting (SEC) code during the state assignment. Such architectures are studied and their characteristics are analyzed for a set of international and industrial FSM benchmarks. The results demonstrate that one of these architectures leads in some cases to implementation with less hardware overhead than TMR and should actually be considered for some types of circuits.